Trenched shield gate power semiconductor devices and methods of manufacture

• US 7,982,265 B2
• Filed: 01/22/2008
• Issued: 07/19/2011
• Est. Priority Date: 05/20/2003
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Challa, Ashok, Elbanhawy, Alan, Sapp, Steven P., Wilson, Peter H., Sani, Babak S., Kocon, Christopher B.
• Primary Examiner(s): Jackson, Jr., Jerome
• Application Number:
  US12/018,166
• Publication Number:
  US 20080150020A1
• Time in Patent Office: 1,274 Days
• Field of Search: 257/341
• US Class Current: 257/341
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region. The charge control trench can be lined with a layer of dielectric material and substantially filled with conductive material. The active trench can include a second shield electrode made of conductive material disposed below the first shield electrode. The first conductive layer inside the active trench can form a secondary gate electrode that is configured to be electrically biased to a desired potential. The semiconductor device can also include a Schottky structure formed between the charge control trench and a second adjacent charge control trench.

Claims

1. A semiconductor device comprising:

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending through the well region and into the drift region, the active trench having its sidewalls and bottom lined with dielectric material, and substantially filled with a first conductive layer and a second conductive layer, the second conductive layer forming a gate electrode and being disposed above the first conductive layer and separated therefrom by inter-electrode dielectric material;

source regions having the first conductivity type formed in the well region adjacent the active trench;

a charge control trench extending deeper into the drift region than the active trench and substantially filled with material to allow for vertical charge control in the drift region;

wherein the charge control trench is lined with a layer of dielectric material and substantially filled with conductive material; and

wherein the active trench further comprises a third conductive layer disposed below the first conductive layer, the third conductive layer is smaller than the first conductive layer.

2. A semiconductor device comprising:

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending through the well region and into the drift region, the active trench having its sidewalls and bottom lined with dielectric material, and substantially filled with a first conductive layer and a second conductive layer, the second conductive layer forming a gate electrode and being disposed above the first conductive layer and separated therefrom by inter-electrode dielectric material, the first conductive layer forming a first shield electrode;

source regions having the first conductivity type formed in the well region adjacent the active trench;

a charge control trench extending deeper into the drift region than the active trench and substantially filled with material to allow for vertical charge control in the drift region; and

wherein the active trench further comprises a second shield electrode made of conductive material disposed below the first shield electrode, the second shield electrode is smaller than the first shield electrode.

3. The semiconductor device of claim 2 wherein the first and second shield electrodes vary in thickness.

4. The semiconductor device of claim 2 wherein the first and second shield electrodes are configured to be independently biased.

5. A semiconductor device comprising:

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending through the well region and into the drift region, the active trench having its sidewalls and bottom lined with dielectric material, and substantially filled with a first conductive layer and a second conductive layer, the second conductive layer forming a gate electrode and being disposed above the first conductive layer and separated therefrom by inter-electrode dielectric material;

source regions having the first conductivity type formed in the well region adjacent the active trench;

a charge control trench extending deeper into the drift region than the active trench and substantially filled with material to allow for vertical charge control in the drift region;

wherein the charge control trench is substantially filled with dielectric material; and

wherein the active trench further comprises a third conductive layer disposed below the first conductive layer, the third conductive layer is smaller than the first conductive layer.

6. The semiconductor device of claim 5 further comprising a lining of second conductivity material extending along exterior sidewalls of the charge control trench.

7. A semiconductor device comprising:

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending through the well region and into the drift region, the active trench having its sidewalls and bottom lined with dielectric material, and substantially filled with a first conductive layer and a second conductive layer, the second conductive layer forming a gate electrode and being disposed above the first conductive layer and separated therefrom by inter-electrode dielectric material;

source regions having the first conductivity type formed in the well region adjacent the active trench;

a charge control trench extending deeper into the drift region than the active trench and substantially filled with material to allow for vertical charge control in the drift region; and

a Schottky structure formed between the charge control trench and a second adjacent charge control trench.

8. A semiconductor device comprising:

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending through the well region and into the drift region, the active trench having its sidewalls and bottom lined with dielectric material, and substantially filled with a first conductive layer and a second conductive layer, the second conductive layer forming a gate electrode and being disposed above the first conductive layer and separated therefrom by inter-electrode dielectric material;

source regions having the first conductivity type formed in the well region adjacent the active trench;

a charge control trench extending deeper into the drift region than the active trench and substantially filled with material to allow for vertical charge control in the drift region;

wherein the first conductive layer inside the active trench forms a secondary gate electrode that is configured to be electrically biased to a desired potential; and

wherein the active trench further comprises a third conductive layer disposed below the first conductive layer, the third conductive layer is smaller than the first conductive layer.

9. The semiconductor device of claim 8 wherein the gate electrode and the secondary gate electrode are configured to be independently electrically biased.

10. The semiconductor device of claim 9 wherein the secondary gate electrode is configured to be biased at a constant potential at approximately the threshold voltage of the semiconductor device.

11. The semiconductor device of claim 9 wherein the secondary gate electrode is configured to be biased at a potential that is greater than a potential applied to the source regions.

12. The semiconductor device of claim 9 wherein the secondary gate electrode is configured to be coupled to a potential at approximately the threshold voltage of the semiconductor device before a switching event.

13. The semiconductor device of claim 8 wherein the charge control trench is lined with a layer of dielectric material and substantially filled with conductive material.

14. The semiconductor device of claim 13 wherein a source electrode is configured to couple the conductive material inside the charge control trench to the source region.

15. The semiconductor device of claim 8 wherein inside the charge control trench is disposed a plurality of conductive layers stacked vertically and separated from each other and from the trench sidewalls by dielectric material.

16. The semiconductor device of claim 15 wherein the plurality of conductive layers inside the charge control trench are configured to be electrically biased to provide vertical charge balancing in the substrate.

17. The semiconductor device of claim 16 wherein the plurality of conductive layers inside the charge control trench are configured to be independently biased.

18. The semiconductor device of claim 15 wherein sizes of the plurality of conductive layers inside the charge control trench vary.

19. The semiconductor device of claim 18 wherein the size of a first conductive layer deeper inside the charge control trench is smaller than the size of a second conductive layer that is disposed above the first conductive layer.

20. The semiconductor device of claim 8 wherein the charge control trench is substantially filed with dielectric material.

21. The semiconductor device of claim 20 further comprising a lining of second conductivity material extending along exterior sidewalls of the charge control trench.

23. The semiconductor device of claim 8 wherein the third conductive layer is isolated from the secondary gate electrode and the trench sidewalls and bottom by dielectric material, the third conductive layer forming a shield electrode that is configured to be electrically biased to a desired potential.

22. A semiconductor device comprising

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending through the well region and into the drift region, the active trench having its sidewalls and bottom lined with dielectric material, and substantially filled with a first conductive layer and a second conductive layer, the second conductive layer forming a gate electrode and being disposed above the first conductive layer and separated therefrom by inter-electrode dielectric material;

source regions having the first conductivity type formed in the well region adjacent the active trench;

a charge control trench extending deeper into the drift region than the active trench and substantially filled with material to allow for vertical charge control in the drift region; and

a Schottky structure formed between the charge control trench and a second adjacent charge control trench;

wherein the first conductive layer inside the active trench forms a secondary gate electrode that is configured to be electrically biased to a desired potential.