Three-dimensionally stacked nonvolatile semiconductor memory

• US 7,983,084 B2
• Filed: 09/03/2009
• Issued: 07/19/2011
• Est. Priority Date: 10/21/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tokiwa, Naoya, Mukai, Hideo
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): Huang; Min
• Application Number:
  US12/553,266
• Publication Number:
  US 20100097858A1
• Time in Patent Office: 684 Days
• Field of Search: 365/185.11, 365/185.05, 365/185.23, 365/185.18, 365/185.24
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.

Claims

1. A three-dimensionally stacked nonvolatile semiconductor memory comprising:

a memory cell array provided in a semiconductor substrate;

three or more first conductive layers stacked on the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another;

three or more second conductive layers which are adjacent to the first conductive layers in a first direction and which are stacked on the semiconductor substrate in the memory cell array in such a manner as to be insulated from one another;

a straight bit line which is disposed on the first and second conductive layers in such a manner as to be insulated from the first and second conductive layers and which extends in the first direction;

a straight source line which is provided between the bit line and the uppermost second conductive layer and which extends in a second direction intersecting with the first direction;

a first semiconductor column which extends through the plurality of first conductive layers and which has an upper end connected to the bit line;

a second semiconductor column which extends through the plurality of second conductive layers and which has an upper end connected to the source line and a lower end connected to the first semiconductor column;

two or more first straight word lines for which the conductive layers among the three or more first conductive layers except for the uppermost conductive layer are used and which extend in the second direction;

two or more second straight word lines for which the conductive layers among the three or more second conductive layers except for the uppermost conductive layer are used and which extend in the second direction;

memory cells provided at intersections of the two or more first word lines and the first semiconductor column and at intersections of the two or more second word lines and the second semiconductor column, respectively;

a register circuit which retains operation setting information for the memory cell array and which has information to supply a potential suitable for each of the first and second word lines; and

a potential control circuit which controls the potentials supplied to the first and second word lines and which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.

2. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the register circuit has two or more registers which retain potential codes indicating the potentials suitable for the two or more first word lines, respectively, and

the potential control circuit selects the potential code corresponding to the input address signal from the two or more registers, and supplies the suitable potential to the word line corresponding to the input address signal in accordance with the selected potential code.

3. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the register circuit has

a first register which retains, as a reference code, a value indicating the potential suitable for one of the two or more first word lines, and

one or more second registers which are respectively provided to correspond to the remaining first word lines except for the word line corresponding to the reference code and which retain a difference code between the reference code and a value indicating the potential suitable for each of the remaining word lines;

and

the potential control circuit selects the difference code corresponding to the input address signal from the one or more second registers, and supplies the suitable potential to a word line corresponding to the input address signal in accordance with a calculation result obtained from the selected difference code and the reference code.

4. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the register circuit has first and second registers which retain first and second coefficients of an approximation function, respectively, and

the potential control circuit uses the input address signal as a variable of the approximation function, and supplies the suitable potential to the first word line corresponding to the input address signal in accordance with the approximation function using the first and second coefficients.

5. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, further comprising:

an external device which externally controls the operation of the memory cell array,

wherein the potential suitable for each of the two or more first word lines is set by an instruction from the external device.

6. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the potential control circuit has

an arithmetic unit which outputs a value indicating the potential supplied to the one word line in accordance with an output of the register circuit and the address signal,

a converter which outputs a converted value of the value indicating the potential supplied to the one word line,

a comparator which outputs a comparison value between a reference value and the converted value, and

a potential generator which generates a potential suitable for each of the word lines in accordance with the comparison value.

7. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, further comprising:

a plate-shaped third conductive layer provided between the lowermost first and second conductive layers and the semiconductor substrate; and

a joint portion which is provided in the third conductive layer and which electrically connects the first semiconductor column to the second semiconductor column,

wherein the third conductive layer functions as a gate electrode of a transistor which uses the joint portion as a channel area.

8. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the uppermost conductive layer among the first conductive layers is a straight first select gate line extending in the second direction, and

the uppermost conductive layer among the second conductive layers is a straight second select gate line extending in the second direction.

9. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the potential supplied to an upper one of the two or more first word lines is equal to or more than the potential supplied to a lower one of the first word lines.

10. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

an upper one of the two or more second word lines is supplied with a potential of the same intensity as the potential supplied to the upper one of the first word lines, and a lower one of the two or more second word lines is supplied with a potential of the same intensity as the potential supplied to the lower one of the first word lines.

11. The three-dimensionally stacked nonvolatile semiconductor memory according to claim 1, wherein

the memory cell has an insulating film functioning as a charge storage layer.