Simulation circuit of PCI express endpoint and downstream port for a PCI express switch

• US 7,983,888 B2
• Filed: 03/21/2005
• Issued: 07/19/2011
• Est. Priority Date: 03/19/2004
• Status: Expired due to Fees

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Rose, Jerry Michael, Evoy, David R.
• Primary Examiner(s): Frejd; Russell
• Application Number:
  US10/592,191
• Publication Number:
  US 20080256284A1
• Time in Patent Office: 2,311 Days
• Field of Search: 703/13, 703/14, 370/463, 710/316, 713/300
• US Class Current: 703/14
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

Single hardware subsystems that present two software views that appear to be two separate hardware subsystems attached in a hierarchy are implemented with PCI arrangements. In an embodiment, a hardware arrangement is configured to emulate two virtually separate hierarchical subsystems in a single hardware block. This emulation facilitates the coupling of devices to PCI Express communications links while addressing PCI-Express linking requirements for such devices.

Claims

1. An integrated endpoint device comprising:

PCI Express endpoint circuitry configured and arranged to perform external PCI Express endpoint device block functions;

PCI Express downstream port circuitry for communicating with a PCI Express bus and configured and arranged to perform downstream port functions; and

simulation circuitry configured to simulate a PCI Express-compliant link between a PCI Express endpoint device and a PCI Express downstream port as respectively implemented by the PCI Express endpoint circuitry and the PCI Express downstream port circuitry.

2. The device of claim 1, further comprising:

a merged configuration register configured to store information for use by the simulation circuitry and the PCI Express Endpoint circuit, the stored information facilitating the simulation of the PCI Express-compliant link.

3. The device of claim 1, wherein the simulation circuitry is configured to interface with software-implemented applications for simulating the PCI Express endpoint circuitry as an external block having a dedicated PCI Express link.

4. The device of claim 1, further comprising at least one non-functional register that is configured to simulate a register that characterizes a PCI Express-compliant device.

5. The device of claim 4, wherein the simulation circuitry is configured to implement the at least one non-functional register for PCI-Express type communications between the integrated endpoint device and a PCI-Express type communications link requiring the implementation of a register function to which the at least one non-functional register is implemented.

6. The device of claim 4, wherein the at least one non-functional register is configured to read only all zeros.

7. The device of claim 4, wherein the non-functional register is simulated to appear to exist from a software perspective.

8. The device of claim 4, wherein at least one non-functional register is unique to each external PCI Express Endpoint device block for which the PCI Express endpoint circuitry performs external functions.

9. The device of claim 4, wherein at least one non-functional register is unique to each simulated PCI Express-compliant link.

10. The device of claim 4, wherein at least one non-functional register is shared between at least two simulated PCI Express-compliant links.

11. The device of claim 1, wherein PCI Express endpoint circuitry is configured and arranged to perform PCI Express Endpoint device block functions for at least two PCI Express Endpoint blocks and wherein the simulation circuitry is configured to simulate and control a virtual link between the at least two PCI Express Endpoint blocks.

12. The device of claim 1, wherein the PCI Express downstream port circuitry is configured to communicate with a PCI Express HUB.

13. The device of claim 1, wherein the PCI Express downstream port circuitry is configured to communicate with a PCI Express type link for at least one of:

a personal computer, a server and a network.

14. The device of claim 1, wherein the simulation circuitry is further configured to simulate the PCI Express-compliant link as including a PCI Express to PCI bridge and a PCI bus coupled to a plurality of PCI Express endpoint device blocks implemented by the PCI Express endpoint circuitry.

15. An integrated PCI Express endpoint device configured to appear on an internal bus of a PCI Express switch while facilitating PCI Express compliance, the device comprising:

a hardware block configured and arranged to;

perform functions of a downstream port of a PCI Express switch;

perform functions of an endpoint device; and

emulate a downstream port block and an endpoint device block coupled by a PCI Express-compliant link and with the emulated downstream port block performing the downstream port functions and the emulated endpoint device block performing the endpoint device functions; and

a merged configuration register configured to store information for use by the hardware block in emulating and performing downstream port, endpoint device and PCI Express-compliant link functions.

16. An integrated endpoint device comprising:

external block means for performing external PCI Express Endpoint device block functions;

port means for communicating with a PCI Express bus and configured and for performing PCI Express downstream port functions; and

simulating means for simulating a PCI Express-compliant link between a PCI Express endpoint device and a PCI Express downstream port as respectively implemented by the external block means and the port means.

17. A PCI Express communications system comprising:

a central processor arrangement;

a host bridge configured and arranged to communicate between the central processor arrangement and a PCI Express switch;

a PCI Express switch comprising;

an upstream port;

a bus; and

a plurality of downstream ports;

a PCI Express endpoint device coupled to one of the downstream ports; and

wherein the PCI Express endpoint device and the downstream port to which it is coupled are comprised in a single circuit that emulates the downstream port and the PCI Express endpoint device coupled via a virtual link.

18. The system of claim 17, further comprising a plurality of registers implemented for simulating characteristics of the emulated downstream port and the PCI Express endpoint device.

19. The system of claim 18, wherein at least one of the plurality of registers is a non-functional register implemented for emulating PCI Express-type functions.

20. A PCI Express communications system comprising:

a PCI to PCI Express bridge;

an upstream port;

a plurality of downstream ports; and

wherein the a PCI to PCI Express bridge, the upstream port and the downstream ports are comprised in a circuit that emulates a virtual link between the PCI to PCI Express bridge and the upstream port and that emulates a PCI Express bus linking the plurality of downstream ports with the upstream port.