Cyclical image buffer

• US 7,995,067 B2
• Filed: 03/29/2007
• Issued: 08/09/2011
• Est. Priority Date: 03/29/2007
• Status: Expired due to Fees

• Current Assignee: MobilEye Vision Technologies Ltd. (Intel Corporation)
• Original Assignee: Mobileye Technologies Limited (Intel Corporation)
• Inventors: Navon, Mois
• Primary Examiner(s): Nguyen; Hau H
• Application Number:
  US11/692,941
• Publication Number:
  US 20080239393A1
• Time in Patent Office: 1,594 Days
• Field of Search: 345/537, 345/539, 345530-532, 345/536, 345/56, 345/100
• US Class Current: 345/531
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 2207/10012 Stereo images
• CPC Class Codes: G06T 7/593 from stereo images
• CPC Class Codes: H04N 13/10 Processing, recording or transmission of stereoscopic or multi-view image signals

Abstract

A storage buffer attached to an image processor for stereo image processing. The processor compares a first image and a second image. The storage buffer stores image data of the second image. The storage buffer includes: a data-shifting-hardware mechanism which while the processor compares a patch of the first image to a swath of the second image, the data shifting mechanism using hardware within the storage buffer shifts at least a portion of the swath within the storage buffer. The data-shifting hardware mechanism includes preferably digital multiplexers with respective selectable inputs from adjacent and non-adjacent columns of data within the storage buffer and selectable inputs from adjacent rows of data within the storage buffer.

Claims

1. In a system including an image processor attached to a storage buffer wherein the storage buffer includes a plurality of n columns of data, said columns numbered from zero to N, wherein N is greater than 1, a method for comparison between first image data and second image data, the method comprising the steps of:

(a) comparing a patch of the first image data to a swath of the second image data, the storage buffer storing the swath of the second image data; and

(b) during said comparing, shifting of said swath using a hardware mechanism within the storage buffer, wherein said shifting includes upon each clock cycle of the processor;

(i) moving the data stored in column one into column N; and

(ii) moving the data stored in each of the n columns from column n into column n−

1.

2. The method according to claim 1, wherein the storage buffer includes a plurality of columns of data, said columns numbered from zero to N, wherein for said patch said comparing to said swath is performed M times, wherein M is less than N, further comprising the step of:

(c) upon completing said comparing to said swath, moving at least N−

M+1 columns of data in a single step.

3. The method according to claim 1, further comprising the step of:

(c) upon completing said comparing to said swath, second shifting into the storage buffer a portion of the second image data, wherein said second shifting is performed from a second storage buffer using a second hardware mechanism into the storage buffer thereby completing a second swath in the storage buffer.

4. The method according to claim 3, wherein said second storage buffer includes no more than two columns of second image data, the height of said columns being equal to the height of said swath.

5. A storage buffer attached to a processor, wherein the processor compares a first image and a second image, the storage buffer storing image data of the second image, wherein the storage buffer includes a plurality of n columns of data, said columns numbered from zero to N, wherein N is greater than 1, the storage buffer comprising:

(a) a data-shifting-hardware mechanism which while the processor compares a patch of the first image to a swath of the second image, the data shifting mechanism using hardware within the storage buffer shifts at least a portion of the swath within the storage buffer wherein said data-shifting-hardware mechanism which upon each clock cycle of the processor;

(i) moves the data stored in column one into column N; and

(ii) moves the data stored in each of the n columns from column n into column n−

1.

6. The storage buffer of claim 5, wherein the data-shifting hardware mechanism includes a plurality of digital multiplexers with respective selectable inputs from adjacent columns of data within the storage buffer.

7. The storage buffer of claim 6, wherein said digital multiplexers include a plurality of respective selectable inputs from adjacent rows of data within the storage buffer.

8. The storage buffer of claim 6, wherein said digital multiplexers include a plurality of respective selectable inputs from at least one non-adjacent columns of data within the storage buffer.