Top layers of metal for high performance IC's
First Claim
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1. An integrated circuit chip comprising:
- a silicon substrate;
multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said passivation layer comprises a nitride layer;
a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, wherein a fourth opening in said polymer layer is over said second contact point, wherein said polymer layer has a thickness between 2 and 30 micrometers; and
a second metallization structure over said polymer layer and said first and second contact points, wherein said first contact point is connected to said second contact point though said second metallization structure, wherein said second metallization structure is configured to be wirebonded.
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Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
562 Citations
56 Claims
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1. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said passivation layer comprises a nitride layer; a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, wherein a fourth opening in said polymer layer is over said second contact point, wherein said polymer layer has a thickness between 2 and 30 micrometers; and a second metallization structure over said polymer layer and said first and second contact points, wherein said first contact point is connected to said second contact point though said second metallization structure, wherein said second metallization structure is configured to be wirebonded. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said passivation layer comprises a nitride layer; and a signal interconnect over said passivation layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said signal interconnect, wherein said signal interconnect comprises electroplated copper. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said passivation layer comprises a nitride layer; a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, and wherein a fourth opening in said polymer layer is over said second contact point, wherein said polymer layer has a thickness between 2 and 30 micrometers; and a signal interconnect on said polymer layer and over said first and second contact points, wherein said first contact point is connected to said second contact point though said signal interconnect. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and over said silicon substrate, wherein said multiple devices comprise a transistor; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a separating layer over said first and second dielectric layers and said first metallization structure, wherein a first opening in said separating layer is over a contact point of said first metallization structure, and said contact point is at a bottom of said first opening; a second metallization structure over said separating layer and on said contact point, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer and vertically over said contact point, wherein said third metal layer is connected to said contact point through said first opening, wherein said second metallization structure comprises aluminum over said separating layer; a first polymer layer between said third and fourth metal layers, wherein said third metal layer is connected to said fourth metal layer through a second opening in said first polymer layer; and a second polymer layer over said fourth metal layer. - View Dependent Claims (32, 33, 34, 35)
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36. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and over said silicon substrate, wherein said multiple devices comprise a transistor; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a separating layer over said first and second dielectric layers and said first metallization structure, wherein a first opening in said separating layer is over a contact point of said first metallization structure, and said contact point is at a bottom of said first opening, wherein said separating layer comprises a nitride layer with a thickness between 0.5 and 2 micrometers, wherein said first opening has a width between 0.5 and 3 micrometers; a second metallization structure over said separating layer and on said contact point, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer and vertically over said contact point, wherein said third metal layer is connected to said contact point through said first opening, wherein said second metallization structure comprises electroplated copper over said separating layer; and a first polymer layer between said third and fourth metal layers, wherein said third metal layer is connected to said fourth metal layer through a second opening in said first polymer layer. - View Dependent Claims (37, 38)
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39. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor; a first dielectric layer over said silicon substrate; a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer; a second dielectric layer between said first and second metal layers; a passivation layer over said first metallization structure and said first and second dielectric layers, wherein a first opening in said passivation layer is over a first contact point of a first metal interconnect of said first metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of a second metal interconnect of said first metallization structure, and said second contact point is at a bottom of said second opening, wherein said first metal interconnect has a portion spaced apart from said second metal interconnect, wherein said passivation layer comprises a nitride layer; a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, and wherein a fourth opening in said polymer layer is over said second contact point, wherein said polymer layer has a thickness between 2 and 30 micrometers; a second metallization structure on said polymer layer and said first and second contact points, wherein said first contact point is connected to said second contact point through said second metallization structure, wherein said second metallization structure comprises aluminum; and an interconnect bump on said second metallization structure. - View Dependent Claims (40, 41, 42, 43)
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44. An integrated circuit chip comprising:
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a silicon substrate; multiple devices in and on said silicon substrate, wherein said multiple devices comprise a transistor; a first dielectric layer over said silicon substrate; a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated copper; a second dielectric layer between said first and second metal layers; a separating layer over said metallization structure and said first and second dielectric layers, wherein multiple openings in said separating layer are over multiple first contact points of said metallization structure, and said multiple first contact points are at bottoms of said multiple openings, wherein said multiple first contact points have a particular common electrical function, wherein said separating layer comprises a nitride layer; and a metal interconnect over said separating layer and on said multiple first contact points, wherein said multiple first contact points are connected to each other through said metal interconnect, wherein said metal interconnect comprises multiple second contact points having said particular common electrical function, wherein said metal interconnect comprises aluminum. - View Dependent Claims (45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56)
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Specification