High speed filter

• US 8,001,172 B2
• Filed: 01/27/2006
• Issued: 08/16/2011
• Est. Priority Date: 01/29/2001
• Status: Expired due to Fees

• Current Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Original Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Inventors: Mallinson, Martin
• Primary Examiner(s): Mai; Tan V
• Application Number:
  US11/340,933
• Publication Number:
  US 20060123075A1
• Time in Patent Office: 2,027 Days
• Field of Search: 708/819, 708/3, 708/5
• US Class Current: 708/819
• CPC Class Codes: G06G 7/1928 for forming correlation integrals; for forming convolution integrals G06G7/195, G06G7/1907 and G06G7/1914 take precedence
• CPC Class Codes: H03H 15/00 Transversal filters electromechanical filters H03H9/46, H03H9/70

Abstract

An electronic filter operates as a correlator that provides a discrete approximation of an analog signal. The analog to digital conversion is integrated directly approximation calculation. An array of sample and hold circuits or single bit comparators provide outputs to a series of multipliers, the other input of which is a coefficient value of a Fourier series approximation of the desired frequency response. Each of the sample and hold circuits samples sequentially in time and holds its sample until the next cycle. Thus the sample point rotates in time through the array and each new sample is multiplied by a different coefficient. The output of the multipliers is summed for evaluation.

Claims

1. A circuit for correlating an input signal comprising:

a parallel array of processing elements, each of said processing elements comprising an analog sampling circuit configured to sample the input signal in response to a timing signal, and a circuit for scaling the resulting sample according to a scaling factor to produce a scaled signal,

wherein the scaling factors in successive processing elements correspond to the coefficients in a Fourier series approximation of a desired frequency response;

a timing circuit for causing the scaled signal to be presented in time-delayed succession to be successive sampled by the analog input circuit, said timing circuit comprising a timing element in parallel with an associated input sample,

wherein the timing circuit is configured to cause the timing signal to be presented in time-delayed succession to successive ones of said analog sampling unit processing elements, said timing circuit comprising a timing element in parallel with an associated analog sampling unit processing element, and said timing element comprising a phase lock loop or a delay lock loop; and

a multiplier configured to multiply the scaled signal and produce an output

wherein the multiplier includes each analog sample unit processing element to scale the output and sum the scaled outputs of said processing elements.

2. A circuit according to claim 1, the multiplier comprising means for multiplying the output of each analog sample unit processing element to scale the output and summing the scaled outputs of said processing elements.

3. A circuit according to claim 1, wherein said timing circuit includes a plurality of elements, where each element includes one of a phase lock loop and a delay lock loop.

4. A circuit according to claim 1, wherein the scaling factor is predetermined.

5. A circuit as in claim 1 wherein said timing circuit comprises a plurality of delay elements, the outputs of which are presented to successive ones of said processing elements.

6. A circuit as in claim 1 wherein said circuit for scaling comprises a multiplier having as inputs the output of said sampling circuit and a predetermined scaling factor, the outputs of said multipliers being summed.

7. A circuit as in claim 1 wherein the scaling factors in successive processing elements correspond to the coefficients in a Fourier series approximation of a desired frequency response, said timing circuit comprises a plurality of delay elements, the outputs of which are presented to successive ones of said processing elements, and said circuit for scaling comprises a multiplier having as inputs the output of said sampling circuit and a predetermined scaling factor, the outputs of said multipliers being summed.

8. A circuit for correlating an input signal comprising:

a parallel array of processing elements, each of said processing elements comprising an analog sampling circuit configured to sample the input signal in response to a timing signal, and a circuit for scaling the resulting sample according to a scaling factor to produce a scaled signal,

wherein the scaling factors in successive processing elements correspond to coefficients in a Fourier series approximation of a desired frequency response, and said circuit for scaling comprises a multiplier having as inputs the output of said sampling circuit and a predetermined scaling factor, the outputs of said multipliers being summed,

a timing circuit for causing the scaled signal to be presented in time-delayed succession to be successive sampled by the analog input circuit, said timing circuit comprising a timing element in parallel with an associated input sample,

wherein the timing circuit is configured to cause the timing signal to be presented in time-delayed succession to successive ones of said analog sampling unit processing elements, said timing circuit comprising a timing element in parallel with an associated analog sampling unit processing element, and said timing element comprising a phase lock loop or a delay lock loop

said timing circuit comprises a plurality of delay elements, the outputs of which are presented to successive ones of said processing elements; and

a multiplier configured to multiply the scaled signal and produce an output,

wherein the multiplier includes each analog sample unit processing element to scale the output and sum the scaled outputs of said processing elements.

9. A circuit according to claim 8, the multiplier comprising means for multiplying the output of each analog sample unit processing element to scale the output and summing the scaled outputs of said processing elements.

10. A circuit according to claim 8, wherein said timing circuit includes a plurality of elements, where each element includes one of a phase lock loop and a delay lock loop.

11. A circuit according to claim 8, wherein the scaling factor is predetermined.

12. A circuit as in claim 8 wherein said timing circuit comprises a plurality of delay elements, the outputs of which are presented to successive ones of said processing elements.

13. A circuit as in claim 8 wherein said circuit for scaling comprises a multiplier having as inputs the output of said sampling circuit and a predetermined scaling factor, the outputs of said multipliers being summed.