Command interface systems and methods

• US 8,005,995 B2
• Filed: 08/16/2007
• Issued: 08/23/2011
• Est. Priority Date: 08/16/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Yamamoto, Tadashi, Ito, Yutaka
• Primary Examiner(s): Lee; Chun-Kuan
• Assistant Examiner(s): MODO, RONALD T
• Application Number:
  US11/840,074
• Publication Number:
  US 20090049455A1
• Time in Patent Office: 1,468 Days
• Field of Search: 710/5, 365/222, 365/233
• US Class Current: 710/5
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling

Abstract

Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

Claims

1. A method comprising:

executing internal commands in an electronic device, the internal commands being carried by internal command signals during a first mode of operation of the electronic device;

receiving external command signals in the electronic device to indicate an end of the first mode;

suspending the execution of commands comprising the internal commands and external commands during a transfer period; and

executing the external commands in the electronic device during a second mode of operation following the transfer period, the external commands being carried by the external command signals.

2. The method of claim 1, wherein executing internal commands includes executing internal commands in a memory device during a sleep mode of operation including parity bit generation and error correction.

3. The method of claim 2, further comprising ending the sleep mode of operation following a change in the external command signals.

4. The method of claim 1, wherein suspending the execution of commands includes suspending the execution of commands when an internal chip select signal operates to disable a command decoder in the electronic device.

5. The method of claim 1, wherein suspending the execution of commands includes suspending the execution of commands when an internal active low chip select signal is high to disable a command decoder in the electronic device.

6. The method of claim 1, wherein executing internal commands includes executing the internal commands in a dynamic random access memory device.

7. The method of claim 1, further comprising receiving the external command signals in the electronic device including receiving:

a clock signal;

a clock enable signal to instruct the validity of the clock signal;

a row address strobe signal to capture an address input and open a row in a memory device corresponding to the address input;

a column address strobe signal to capture an address input and select a column in the memory device corresponding to the address input;

a chip select signal to enable a command decoder in the memory device;

a write enable signal to determine whether the column address strobe signal initiates a read operation or a write operation; and

a data-mask signal to control data input and data output between the memory device and a data bus.

8. The method of claim 1, further comprising generating the internal command signals in the electronic device including generating:

a row address strobe signal to capture an address input and open a row in a memory device corresponding to the address input;

a column address strobe signal to capture an address input and select a column in the memory device corresponding to the address input;

a write enable signal to determine whether the column address strobe signal initiates a read operation or a write operation; and

a chip select signal to enable a command decoder in the memory device.

9. A method comprising:

executing internal commands with a command decoder in a memory device;

disabling the command decoder during a transfer period; and

executing external commands with the command decoder in the memory device following the transfer period.

10. The method of claim 9, wherein disabling the command decoder includes generating an internal chip select signal in the memory device to disable the command decoder during the transfer period.

11. The method of claim 9, wherein disabling the command decoder includes generating an internal chip select signal in the memory device to be active during the transfer period to disable the command decoder.

12. The method of claim 9, wherein disabling the command decoder includes generating an internal active low chip select signal in the memory device to be high during the transfer period to disable the command decoder.

13. The method of claim 9, wherein executing internal commands includes:

generating an internal chip select signal;

generating an internal row address strobe signal;

generating an internal column address strobe signal;

generating an internal write enable signal; and

executing commands indicated by the internal chip select signal, the internal row address strobe signal, the internal column address strobe signal, and the internal write enable signal.

14. The method of claim 9, wherein executing internal commands includes executing internal commands with a command decoder in a dynamic random access memory device.

15. The method of claim 9, wherein executing external commands includes executing commands carried by:

an external clock signal;

an external clock enable signal;

an external chip select signal;

an external row address strobe signal;

an external column address strobe signal;

an external write enable signal; and

an external data-mask signal.

16. An apparatus comprising:

a memory device including an array of memory cells;

a command decoder to decode and execute internal commands and external commands with respect to the array of memory cells; and

a controller to generate the internal commands during a first mode of operation, the command decoder to decode and execute the internal commands, the controller to generate an internal command to disable the command decoder during a transfer period between the first mode of operation and a second mode of operation, the command decoder to decode and execute the external commands during the second mode of operation.

17. The apparatus of claim 16, further comprising a circuit to generate an internal chip select signal to disable the command decoder during the transfer period.

18. The apparatus of claim 16, wherein the circuit to generate the internal chip select signal is a logic circuit located in the controller.

19. The apparatus of claim 16, wherein:

the memory device includes a state machine to generate signals to control operations of the memory device during the first mode of operation; and

the controller is an error correcting code controller circuit to generate internal command signals, the command decoder to decode the internal command signals into the internal commands during the first mode of operation.

20. The apparatus of claim 16, further comprising a multiplexer in the memory device to couple the internal commands to the command decoder during the first mode of operation and to couple the external commands to the command decoder during the second mode of operation.

21. The apparatus of claim 20, further comprising a buffer circuit in the memory device to couple external command signals received from a bus to the multiplexer, the external command signals to carry the external commands.

22. The apparatus of claim 16, wherein the memory device is coupled to receive external command signals including:

a clock signal;

a clock enable signal to instruct the validity of the clock signal;

a row address strobe signal to capture an address input and open a row in the array corresponding to the address input;

a column address strobe signal to capture an address input and select a column in the array corresponding to the address input;

a write enable signal to determine whether the column address strobe signal initiates a read operation or a write operation; and

a data-mask signal to control data input and data output between the memory device and a data bus.

23. A system comprising:

a processor coupled to a bus to generate external command signals on the bus;

a dynamic random access memory device including an array of memory cells coupled to the bus to receive the external command signals from the processor, the memory device including;

a command decoder to decode and execute internal command signals and the external command signals; and

a controller to generate the internal command signals during a sleep mode of operation, the controller to disable the command decoder during a transfer period between the sleep mode of operation and a normal mode of operation, the command decoder to decode and execute the external command signals during a normal mode of operation.

24. The system of claim 23, wherein the external command signals include:

a chip select signal;

a clock signal;

a clock enable signal to instruct the validity of the clock signal;

a row address strobe signal to capture an address input and open a row in the array corresponding to the address input;

a column address strobe signal to capture an address input and select a column in the array corresponding to the address input;

a write enable signal to determine whether the column address strobe signal initiates a read operation or a write operation; and

a data-mask signal to control data input and data output between the memory device and a data bus.

25. The system of claim 23, wherein the controller is coupled to the command decoder to generate a high internal chip select signal during the transfer period to disable the command decoder, the internal chip select signal being active low.

26. The system of claim 23, wherein the controller is an error correcting code controller circuit coupled to generate the internal command signals to initiate parity bit generation and error correction during the sleep mode of operation.

27. The system of claim 23, further comprising a display to couple to the processor and to display data.

28. The system of claim 23, further comprising:

a lens; and

an imaging plane to couple to the processor, the imaging plane to receive light captured by the lens.

29. The system of claim 23, further comprising a cellular telephone receiver to receive data, the cellular telephone receiver forming a portion of a wireless transceiver coupled to the processor.

30. The system of claim 23, further comprising a set of media playback controls to couple to the processor.