Fan-out, display substrate having the same and method for manufacturing the display substrate

• US 8,008,665 B2
• Filed: 10/25/2007
• Issued: 08/30/2011
• Est. Priority Date: 01/02/2007
• Status: Active Grant

• Current Assignee: TCL China Star Optoelectronics Technology Co. Ltd. (TCL Technology Group Corp.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, So-Woon, Kim, Yeon-Ju, Chai, Chong-Chul, Shin, Kyoung-Ju, Yang, Sung-Hoon, Yoon, Soo-Wan, Youn, Joo-Ae
• Primary Examiner(s): Lee; Eugene
• Assistant Examiner(s): Ho; Anthony
• Application Number:
  US11/924,111
• Publication Number:
  US 20080157364A1
• Time in Patent Office: 1,405 Days
• Field of Search: 257/59, 257/72, 438/149, 438/151, 349/149, 349/152
• US Class Current: 257/72
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A display substrate having a fan-out and a method for manufacturing the display substrate are disclosed. The fan-out includes an insulating substrate, a first line, a second line, a resistance control pattern, and first and second detour pattern. The first line is disposed on the insulating substrate and is connected to a pad. The second line is formed from the same layer as the first line and is connected to a thin-film transistor (TFT). The resistance control pattern is formed from a different layer than the first and second lines. The first and second detour patterns are formed from a different layer than the first and second lines and the resistance control pattern, and connect the first and second lines with the resistance control pattern, respectively.

Claims

1. A fan-out, comprising:

an insulating substrate;

a first line disposed on the insulating substrate and connected to a pad;

a second line spaced apart from the first line and formed from the same layer as the first line and connected to a thin-film transistor (TFT);

a resistance control pattern formed from a different layer than the first line and the second line; and

a first detour pattern and a second detour pattern spaced apart from the first detour pattern, and the first detour pattern and the second detour pattern being formed from a different layer than the first line, the second line, and the resistance control pattern, the first detour pattern electrically connecting the first line to the resistance control pattern, the second detour pattern electrically connecting the second line to the resistance control pattern so that the first line and the second line are electrically connected to each other through the resistance control pattern.

2. The fan-out of claim 1, wherein the resistance control pattern comprises indium tin oxide (ITO) or indium zinc oxide (IZO).

3. The fan-out of claim 1, wherein the first line is connected to a gate pad, and the second line is connected to a gate electrode of the TFT.

4. The fan-out of claim 1, wherein the first line is connected to a data pad, and the second line is connected to a source electrode of the TFT.

5. The fan-out of claim 1, wherein a resistance control portion comprises the first line, the second line, the first detour pattern, and the second detour pattern, and more than two resistance control portions are connected to each other in series.

6. The fan-out of claim 1, wherein the resistance control pattern is arranged in a zigzag shape.

7. The fan-out of claim 1, further comprising:

a first additional resistance control pattern and a second additional resistance control pattern formed from the same layer as the resistance control pattern,

wherein the first line comprises a first extension portion protruding from the first line, and the second line comprises a second extension portion protruding from the second line, and

wherein the first additional resistance control pattern contacts the first line at the first extension portion, and the second additional resistance control pattern contacts the second line at the second extension portion.

8. The fan-out of claim 1, further comprising:

a first additional resistance control pattern and a second additional resistance control pattern formed from the same layer as the resistance control pattern, the first line and the second line being connected to the first detour pattern and the second detour pattern via the first additional resistance control pattern and the second additional resistance control pattern, respectively.

9. The fan-out of claim 8, wherein the first additional resistance control pattern and the second additional resistance control pattern comprise the same material as the resistance control pattern.

10. The fan-out of claim 8, wherein a resistance control portion comprises the first line, the second line, the first detour pattern, and the second detour pattern, and more than two resistance control portions are connected to each other in series.

11. The fan-out of claim 8, wherein the resistance control pattern is arranged in a zigzag shape.

12. The fan-out of claim 1, wherein a plurality of resistance control patterns connect a plurality of first lines to a plurality of second lines, respectively, and a first resistance control pattern has a different length than a second resistance control pattern.

13. The fan-out of claim 8, wherein the first line comprises a first extension portion protruding from the first line, and the second line comprises a second extension portion protruding from the second line, and

wherein the first additional resistance control pattern contacts the first line at the first extension portion, and the second additional resistance control pattern contacts the second line at the second extension portion.

14. A display substrate, comprising:

a fan-out comprising;

an insulating substrate;

a first line disposed on the insulating substrate and connected to a pad;

a second line spaced apart from the first line and formed from the same layer as the first line and connected to a thin-film transistor;

a resistance control pattern formed from a different layer than the first line and the second line; and

a first detour pattern and a second detour pattern spaced apart from the first detour pattern, and the first detour pattern and the second detour pattern being formed from a different layer than the first line, the second line, and the resistance control pattern, the first detour pattern electrically connecting the first line to the resistance control pattern, the second detour pattern electrically connecting the second line to the resistance control pattern so that the first line and the second line are electrically connected to each other through the resistance control pattern; and

a gate line or a data line connected to the fan-out.

15. The display substrate of claim 14, wherein the first detour pattern and the second detour pattern are formed from substantially a same layer as the gate line or the data line.

16. The display substrate of claim 15, wherein the first detour pattern and the second detour pattern comprise at least one of aluminum, chromium, molybdenum, tantalum, or titanium.

17. The display substrate of claim 14, further comprising:

a first additional resistance control pattern and a second additional resistance control pattern formed from the same layer as the resistance control pattern,

wherein the first line comprises a first extension portion protruding from the first line, and the second line comprises a second extension portion protruding from the second line, and

wherein the first additional resistance control pattern contacts the first line at the first extension portion, and the second additional resistance control pattern contacts the second line at the second extension portion.

18. A method for manufacturing a display substrate, the method comprising:

forming a first line and a second line;

forming a first insulating layer on the first line and the second line;

forming a first contact hole through the first insulating layer to expose the first line or the second line;

forming a first detour pattern connected to the first line through the first contact hole or a second detour pattern connected to the second line through the first contact hole;

forming a second insulating layer on the first detour pattern or the second detour pattern;

forming a second contact hole through the second insulating layer to exposed the first detour pattern or the second detour patter; and

forming a resistance control pattern connected to the first detour pattern or the second detour pattern through the second contact hole.

19. A method for manufacturing a display substrate, the method comprising:

forming a first line and a second line;

forming a first insulating layer on the first line and the second line;

forming a first detour pattern or a second detour pattern on the first insulating layer;

forming a second insulating layer on the first detour pattern or the second detour pattern;

patterning the first insulating layer to form contact holes exposing the first line and the second line, and patterning the second insulating layer to form a contact hole exposing the first detour pattern or the second detour pattern; and

forming a resistance control pattern connected to the first detour pattern or the second detour pattern via the contact hole in the second insulating layer.

20. The method of claim 19, further comprising

forming an additional resistance control pattern connected to the first line or the second line, and the first detour pattern or the second detour pattern.