Sequence control unit, driving method thereof, and liquid crystal display device having the same

• US 8,013,824 B2
• Filed: 09/20/2007
• Issued: 09/06/2011
• Est. Priority Date: 09/21/2006
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chu, Hong Sig, Ha, Jae Min
• Primary Examiner(s): Hjerpe; Richard
• Assistant Examiner(s): PARKER, JEFFREY ALAN
• Application Number:
  US11/858,428
• Publication Number:
  US 20080074375A1
• Time in Patent Office: 1,447 Days
• Field of Search: 345/90, 345/87, 345/94, 345/98, 345/99, 345/100
• US Class Current: 345/90
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A sequence control unit includes a voltage input/output unit to receive a driving voltage, and to output the driving voltage after a delay time. A memory stores an output time corresponding to the driving voltage, a clock generating unit generates a clock, a clock counter counts the clock in response to a counting signal, and a sequence controller supplies the counting signal corresponding to the output timing to the clock counter from the memory. The sequence controller receives the number of clock cycles or time associated with the number of clock cycles counted by the clock counter as clock counting information, and controls the delay time output of the driving voltage according to the clock counting information. A driving method for driving the sequence control unit is disclosed, and the sequence control unit may be included in a liquid crystal display device.

Claims

1. A liquid crystal display device, comprising:

a liquid crystal display panel to display an image;

a panel driving unit configured to drive the liquid crystal display panel in response to panel driving voltages and a control signal;

a timing controller configured to transmit a pixel data signal to the panel driving unit and to generate a control signal in response to a reference voltage;

a direct current/direct current (“

DC/DC”

) converter configured to generate the panel driving voltages and the reference voltage; and

a sequence control unit comprising;

a voltage input/output unit configured to receive the panel driving voltages and the reference voltage from the direct current/direct current converter and to output the panel driving voltages and the reference voltage;

a memory configured to store output timing data signals of the panel driving voltages and the reference voltage;

a clock generating unit configured to generate a clock;

a clock counter configured to count the clock in response to a counting signal, and configured to generate clock counting information; and

a sequence controller configured to receive the output timing data signals of the panel driving voltages and the reference voltage from the memory, to supply the counting signal to the clock counter according to the output timing data signal of each of the panel driving voltages and the reference voltage, to control the voltage input/output unit in response to the clock counting information to delay the output of each of the panel driving voltages and the reference voltage.

2. The liquid crystal display device of claim 1,

wherein the panel driving unit comprises a gate driving unit to drive a gate line of the liquid crystal display panel, a data driving unit to drive a data line of the liquid crystal display panel, and a gamma voltage generating unit to supply a gamma voltage to the data driving unit, and

wherein the panel driving voltages comprise a gate-on voltage and a gate-off voltage to be supplied to the panel driving unit, an initial driving voltage to be supplied to the gate driving unit and the data driving unit, an analog voltage to be supplied to the gamma voltage generating unit, and a common voltage to be supplied to the liquid crystal display panel.

3. The liquid crystal display device of claim 1, wherein a serial clock signal and a serial data signal are transmitted to the memory by serial communications.

4. The liquid crystal display device of claim 3, wherein the memory serially communicates with the timing controller or an external system.

5. The liquid crystal display device of claim 1, wherein an output of the sequence control unit is cut off in response to a shut-down signal supplied to the sequence controller.

6. The liquid crystal display device of claim 1, wherein the clock counting information comprises a number of clock cycles counted by the clock counter or a total time of the clock cycles added by the clock counter.

7. The liquid crystal display device of claim 6, wherein the sequence controller delays the output of each of the panel driving voltages and the reference voltage for the clock counting information corresponding to the output timing data signal of each of the panel driving voltages and the reference voltage.