Memory device, semiconductor device, and electronic device

• US 8,018,755 B2
• Filed: 09/02/2008
• Issued: 09/13/2011
• Est. Priority Date: 09/03/2007
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): Norman; James G
• Application Number:
  US12/202,516
• Publication Number:
  US 20090059650A1
• Time in Patent Office: 1,106 Days
• Field of Search: None
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

To provide a memory device which can maintain data accurately even when memory characteristics of a memory element deteriorate over time. The memory device includes a memory cell 100, a reading circuit 103, a power supply line 104, a first signal line 105, a second signal line 102, and an output terminal 106. The memory cell 100 includes a memory element 108, the resistance value of which is changed and holds data by utilizing the resistance value of the memory element 108. The reading circuit 103 reads data held in the memory cell 100. The output terminal 106 outputs a potential of the power supply line 104 or a potential corresponding to the data held in the memory cell 100 in accordance with the resistance value of the memory element 108. The reading circuit 103 includes a transistor 109 having first to fourth terminals. The threshold voltage of the transistor 109 is controlled by supplying a potential to a channel region through the fourth terminal.

Claims

1. A memory device comprising:

a power supply line;

a first signal line;

a second signal line;

an output terminal;

a reading circuit including a transistor and a clocked inverter; and

a memory cell including a memory element, the memory cell being electrically connected to the second signal line and the reading circuit,

wherein an input terminal of the clocked inverter is electrically connected to the second signal line,

wherein an output terminal of the clocked inverter is electrically connected to the output terminal,

wherein the transistor comprises;

a first terminal electrically connected to the power supply line and serving as one of a source terminal and a drain terminal;

a second terminal electrically connected to the memory cell through the second signal line and serving as the other of the source terminal and the drain terminal;

a third terminal electrically connected to the first signal line and serving as a gate terminal; and

a fourth terminal,

wherein the reading circuit comprises an inverter, wherein an input terminal of the inverter is electrically connected to the first signal line, and

wherein an output terminal of the inverter is electrically connected to the third terminal of the transistor.

2. The memory device according to claim 1, wherein the transistor is turned ON by supplying a first potential to a channel region of the transistor through the third terminal and threshold voltage of the transistor is controlled by supplying a second potential to the channel region through the fourth terminal.

3. The memory device according to claim 1, wherein the memory element includes a first electrode, a second electrode, and an organic compound layer between the first and second electrodes.

4. A memory device comprising:

a power supply line;

a first signal line;

a second signal line;

an output terminal;

a reading circuit including a transistor and a clocked inverter; and

a memory cell including a memory element, and the memory cell being electrically connected to the second signal line and the reading circuit,

wherein the reading circuit is electrically connected to the power supply line, the first signal line, the second signal line,

wherein an input terminal of the clocked inverter is electrically connected to the second signal line,

wherein an output terminal of the clocked inverter is electrically connected to the output terminal,

wherein the transistor comprises;

a first gate electrode;

a second gate electrode;

a semiconductor layer between the first and second gate electrodes, the semiconductor layer including a source region, a drain region, and a channel region between the source and drain regions;

a first gate insulating film between the first gate electrode and the semiconductor layer; and

a second gate insulating film between the second gate electrode and the semiconductor layer,

wherein the reading circuit comprises an inverter, wherein an input terminal of the inverter is electrically connected to the first signal line, and

wherein an output terminal of the inverter is electrically connected to the first gate electrode of the transistor.

5. The memory device according to claim 4, wherein the transistor is turned ON by supplying a first potential to the channel region through the first gate electrode and threshold voltage of the transistor is controlled by supplying a second potential to the channel region through the second gate electrode.

6. The memory device according to claim 4, wherein the memory element includes a first electrode, a second electrode, and an organic compound layer between the first and second electrodes.

7. A memory device comprising:

a power supply line;

a first signal line;

a second signal line;

an output terminal;

a reading circuit including a transistor and a clocked inverter; and

a memory cell including a memory element, and the memory cell being electrically connected to the second signal line and the reading circuit,

wherein the reading circuit is electrically connected to the power supply line, the first signal line, the second signal line,

wherein an input terminal of the clocked inverter is electrically connected to the second signal line,

wherein an output terminal of the clocked inverter is electrically connected to the output terminal,

wherein the transistor comprises;

a semiconductor substrate including a first impurity region serving as one of a source region and a drain region, a second impurity region serving as the other of the source region and the drain region, a channel region between the first and second impurity regions, and a third impurity region; and

a gate electrode over the channel region with a gate insulating film interposed therebetween,

wherein the reading circuit comprises an inverter, wherein an input terminal of the inverter is electrically connected to the first signal line, and

wherein an output terminal of the inverter is electrically connected to the gate electrode of the transistor.

8. The memory device according to claim 7, wherein the transistor is turned ON by supplying a first potential to the channel region through the gate electrode and threshold voltage of the transistor is controlled by supplying a second potential to the channel region through the third impurity region.

9. The memory device according to claim 7, wherein the memory element includes a first electrode, a second electrode, and an organic compound layer between the first and second electrodes.

10. A semiconductor device comprising:

an antenna;

a high frequency circuit electrically connected to the antenna; and

a logic circuit comprising a memory device, electrically connected to the high frequency circuit,

the memory device comprising;

a power supply line;

a first signal line;

a second signal line;

an output terminal;

a reading circuit including a transistor and a clocked inverter; and

a memory cell including a memory element, the memory cell being electrically connected to the second signal line and the reading circuit,

wherein an input terminal of the clocked inverter is electrically connected to the second signal line,

wherein an output terminal of the clocked inverter is electrically connected to the output terminal,

wherein the transistor comprises;

a first terminal electrically connected to the power supply line and serving as one of a source terminal and a drain terminal;

a second terminal electrically connected to the memory cell through the second signal line and serving as the other of the source terminal and the drain terminal;

a third terminal electrically connected to the first signal line and serving as a gate terminal; and

a fourth terminal,

wherein the reading circuit comprises an inverter, wherein an input terminal of the inverter is electrically connected to the first signal line, and

wherein an output terminal of the inverter is electrically connected to the third terminal of the transistor.

11. The memory device according to claim 10, wherein the transistor is turned ON by supplying a first potential to a channel region of the transistor through the third terminal and threshold voltage of the transistor is controlled and by supplying a second potential to the channel region through the fourth terminal.

12. The memory device according to claim 10, wherein the memory element includes a first electrode, a second electrode, and an organic compound layer between the first and second electrodes.

13. The semiconductor device according to claim 10, wherein the semiconductor device is incorporated into an electronic device selected from the group consisting of a liquid crystal display devices, an EL display devices, a television set, and a mobile phone.

14. A semiconductor device comprising:

an antenna;

a high frequency circuit electrically connected to the antenna; and

a logic circuit comprising a memory device, electrically connected to the high frequency circuit,

the memory device comprising;

a power supply line;

a first signal line;

a second signal line;

an output terminal;

a reading circuit including a transistor and a clocked inverter; and

a memory cell including a memory element, the memory cell being electrically connected to the second signal line and the reading circuit,

wherein the reading circuit is electrically connected to the power supply line, the first signal line, the second signal line,

wherein an input terminal of the clocked inverter is electrically connected to the second signal line,

wherein an output terminal of the clocked inverter is electrically connected to the output terminal,

wherein the transistor comprises;

a first gate electrode;

a second gate electrode;

a semiconductor layer between the first and second gate electrodes, the semiconductor layer including a source region, a drain region, and a channel region between the source and drain regions;

a first gate insulating film between the first gate electrode and the semiconductor layer; and

a second gate insulating film between the second gate electrode and the semiconductor layer,

wherein the reading circuit comprises an inverter, wherein an input terminal of the inverter is electrically connected to the first signal line, and

wherein an output terminal of the inverter is electrically connected to the first gate electrode of the transistor.

15. The memory device according to claim 14, wherein the transistor is turned ON by supplying a first potential to the channel region through the first gate electrode and threshold voltage of the transistor is controlled by supplying a second potential to the channel region through the second gate electrode.

16. The memory device according to claim 14, wherein the memory element includes a first electrode, a second electrode, and an organic compound layer between the first and second electrodes.

17. The semiconductor device according to claim 14, wherein the semiconductor device is incorporated into an electronic device selected from the group consisting of a liquid crystal display devices, an EL display devices, a television set, and a mobile phone.

18. A semiconductor device comprising:

an antenna;

a high frequency circuit electrically connected to the antenna; and

a logic circuit comprising a memory device, electrically connected to the high frequency circuit,

the memory device comprising;

a power supply line;

a first signal line;

a second signal line;

an output terminal;

a reading circuit including a transistor and a clocked inverter; and

a memory cell including a memory element, the memory cell being electrically connected to the second signal line and the reading circuit,

wherein the reading circuit is electrically connected to the power supply line, the first signal line, the second signal line,

wherein an input terminal of the clocked inverter is electrically connected to the second signal line,

wherein an output terminal of the clocked inverter is electrically connected to the output terminal,

wherein the transistor comprises;

a semiconductor substrate including a first impurity region serving as one of a source region and a drain region, a second impurity region serving as the other of the source region and the drain region, a channel region between the first and second impurity regions, and a third impurity region; and

a gate electrode over the channel region with a gate insulating film interposed therebetween,

wherein the reading circuit comprises an inverter, wherein an input terminal of the inverter is electrically connected to the first signal line, and

wherein an output terminal of the inverter is electrically connected to the gate electrode of the transistor.

19. The memory device according to claim 18, wherein the transistor is turned ON by supplying a first potential to the channel region through the gate electrode and threshold voltage of the transistor is controlled by supplying a second potential to the channel region through the third impurity region.

20. The memory device according to claim 18, wherein the memory element includes a first electrode, a second electrode, and an organic compound layer between the first and second electrodes.

21. The semiconductor device according to claim 18, wherein the semiconductor device is incorporated into an electronic device selected from the group consisting of a liquid crystal display devices, an EL display devices, a television set, and a mobile phone.