Method and apparatus for on-demand power management

• US 8,020,015 B2
• Filed: 05/23/2008
• Issued: 09/13/2011
• Est. Priority Date: 12/21/2004
• Status: Expired due to Fees

• Current Assignee: Packet Digital, LLC
• Original Assignee: Packet Digital, LLC
• Inventors: Morlock, Brian M., Kakumanu, Divyata, Jorgenson, Joel A.
• Primary Examiner(s): Stoynov; Stefan
• Application Number:
  US12/126,213
• Publication Number:
  US 20080263377A1
• Time in Patent Office: 1,208 Days
• Field of Search: 713/320, 713/322, 702/60, 703/17, 703/22, 455/574
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system.

Claims

1. An apparatus, comprising:

a system controller to monitor an application processing demand on a processing system and to determine one or more clock frequencies and one or more voltages at which the processing system operates;

a power distribution manager coupled with the system controller to provide one or more operating voltages to the processing system and to switch between a first one or more voltages and a second one or more voltages without halting the processing system; and

a clock domain manager coupled with the system controller to provide one or more clock signals to the processing system and to switch between a first one or more clock frequencies and a second one or more clock frequencies without halting the processing system, wherein

the first one or more clock frequencies and the second one or more clock frequencies are phase-locked to a common reference frequency, and wherein

the second one or more clock frequencies are phase-matched to the first one or more clock frequencies.

2. The apparatus of claim 1, wherein the system controller comprises:

a bus interface unit to monitor activity on a system bus and to select an operating point for the processing system;

a programmable memory, coupled with the bus interface unit, including a programmed table to correlate activity on the system bus with the application processing demand; and

a state machine coupled with the bus interface unit to control the provision of voltages in the power distribution manager and the provision of clock frequencies in the clock domain manager.

3. The apparatus of claim 2, the bus interface unit to:

detect a plurality of commands on a system bus;

recognize a command pattern; and

select a new operating point from the programmable memory.

4. The apparatus of claim 2, the bus interface unit to:

detect an average number of processing events per unit time;

compare the average number of processing events per unit time with a current clock frequency; and

select a new operating point from the programmable memory.

5. The apparatus of claim 2, wherein the system controller comprises an interrupt input to receive a commanded mode power setting.

6. The apparatus of claim 1, further comprising:

a processing device coupled with the power distribution manger and the clock domain manager;

a system bus coupled with the processing device and the system controller; and

a memory coupled with the system bus.

7. The apparatus of claim 6, further comprising one or more peripheral devices coupled with the system bus, the power distribution manager and the clock domain manager.

8. The apparatus of claim 7, wherein each peripheral devices comprises one of a single chip device, a multi-chip module and one or more circuit cards.