Expander circuit for a solid state persistent storage device that provides a plurality of interfaces to corresponding storage controllers

• US 8,020,035 B2
• Filed: 09/30/2008
• Issued: 09/13/2011
• Est. Priority Date: 07/30/2008
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Daigle, David Alan, Thiel, David William, Voigt, Douglas L.
• Primary Examiner(s): Wilson; Yolanda L
• Application Number:
  US12/242,022
• Publication Number:
  US 20100083040A1
• Time in Patent Office: 1,078 Days
• Field of Search: 714/4, 714/6, 714/43, 714/4.1, 714/5.1, 710/62, 710/72, 710/74, 710/313, 710/305
• US Class Current: 714/5.1
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 11/2092 Techniques of failing over between control units
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A system includes a solid state persistent storage device, and a plurality of storage controllers to manage access of the solid state persistent storage device. An expander circuit is connected to the solid state persistent storage device and has a plurality of computer-based bus interfaces connected to the corresponding plurality of storage controllers.

Claims

1. An apparatus comprising:

a solid state persistent storage device;

a plurality of storage controllers to manage access of the solid state persistent storage device; and

an expander circuit connected to the solid state persistent storage device and having a plurality of interfaces connected to the corresponding plurality of storage controllers, wherein the plurality of interfaces are computer-based bus interfaces, wherein the expander circuit provides fault tolerance such that failure of one of the storage controllers does not prevent access of data in the solid state persistent storage device.

2. The apparatus of claim 1, further comprising:

a first storage board containing the expander circuit and the solid state persistent storage device; and

a second storage board containing a second expander circuit and a second solid state persistent storage device, the second expander circuit connected to the second solid state persistent storage device and having a plurality of computer-based bus interfaces connected to the corresponding plurality of storage controllers.

3. The apparatus of claim 1, wherein the computer-based bus interfaces comprise Peripheral Component Interconnect (PCI) bus interfaces.

4. The apparatus of claim 1, wherein the solid state persistent storage device comprises one of a flash memory device and a battery-based memory device.

5. The apparatus of claim 1, further comprising another solid state persistent storage device connected to the expander circuit.

6. The apparatus of claim 1, wherein the expander circuit is connected to a particular one of the storage controllers over a Peripheral Component Interconnect (PCI) bus.

7. The apparatus of claim 6, further comprising a PCI expander, wherein the expander circuit is connected to the particular storage controller through the PCI expander and over the PCI bus.

8. An apparatus comprising:

a solid state persistent storage device;

a plurality of storage controllers to manage access of the solid state persistent storage device;

an expander circuit connected to the solid state persistent storage device and having a plurality of interfaces connected to the corresponding plurality of storage controllers, wherein the plurality of interfaces are computer-based bus interfaces;

a first storage board containing the expander circuit and the solid state persistent storage device; and

a second storage board containing a second expander circuit and a second solid state persistent storage device, the second expander circuit connected to the second solid state persistent storage device and having a plurality of computer-based bus interfaces connected to the corresponding plurality of storage controllers,

wherein the first and second storage boards enable error recovery using erasure coding.

9. An apparatus comprising:

a solid state persistent storage device;

a plurality of storage controllers to manage access of the solid state persistent storage device;

an expander circuit connected to the solid state persistent storage device and having a plurality of interfaces connected to the corresponding plurality of storage controllers, wherein the plurality of interfaces are computer-based bus interfaces; and

a plurality of storage boards containing respective expander circuits and solid state persistent storage devices, wherein the plurality of storage boards enable provision of RAID (redundant array of inexpensive disks) redundancy.

10. A method of providing fault tolerance, comprising:

connecting a solid state persistent storage device to an expander circuit;

connecting computer-based bus interfaces of the expander circuit to corresponding ones of a plurality of storage controllers;

programming the expander circuit to communicate with a particular one of the plurality of storage controllers;

detecting failure of the particular storage controller or failure of a storage network connected to the particular storage controller or failure of a link between the particular storage controller and the expander circuit; and

in response to detecting the failure, re-programming the expander circuit to communicate with another one of the plurality of storage controllers.

11. A method of providing fault tolerance, comprising:

connecting a solid state persistent storage device to an expander circuit;

connecting computer-based bus interfaces of the expander circuit to corresponding ones of a plurality of storage controllers;

programming the expander circuit to communicate with a particular one of the plurality of storage controllers;

connecting at least another solid state persistent storage device to another expander circuit; and

performing data error recovery using erasure coding for data stored in the solid state persistent storage devices.