Multiple voltage threshold timing analysis for a digital integrated circuit

• US 8,020,129 B2
• Filed: 01/29/2008
• Issued: 09/13/2011
• Est. Priority Date: 01/29/2008
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: International Business Machines Corporation
• Inventors: Abbaspour, Soroush, Feldmann, Peter
• Primary Examiner(s): Kik; Phallaka
• Application Number:
  US12/021,723
• Publication Number:
  US 20090193373A1
• Time in Patent Office: 1,323 Days
• Field of Search: 716/5, 703/16
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.

Claims

1. A method, performed on a computer system, for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, the method comprising:

using the computer system to perform the following;

obtaining characterization data describing driving behavior of the at least one logic gate, wherein the characterization data is obtained from a circuit-level model of the at least one logic gate and is in a form that approximates a current source, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance;

obtaining a model of the interconnect circuit;

deriving a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit, wherein the deriving of a sequence of crossing times comprises estimating a charge supplied by the at least one logic gate to the interconnect circuit on a piecewise basis at each of the successive voltage thresholds provided in the driving point voltage waveform and determining a dynamic capacitance on a piecewise basis at each of the successive voltage thresholds from the estimated charges, wherein each crossing time is derived as a function of each determined dynamic capacitance and corresponding sequence of voltage thresholds; and

generating a voltage waveform by piecing together the derived sequence of crossing times and the corresponding sequence of voltage thresholds, wherein the generated voltage waveform is a piecewise linear waveform indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit.

2. The method according to claim 1, wherein the obtaining of characterization data comprises accessing a library containing a plurality of tables representing the at least one logic gate loaded by various pure capacitive loads and excited by voltage waveforms of varying slew rates.

3. The method according to claim 1, wherein the obtaining of the model of the interconnect circuit comprises obtaining a reduced ordered model that is represented in a pole/residue form.

4. The method according to claim 1, further comprising using the generated voltage waveform to perform a timing analysis of the digital integrated circuit.

5. The method according to claim 4, further comprising determining the timing of an entire path of the digital integrated circuit.

6. A computer-readable storage device storing computer instructions, which when executed, enables a computer system to perform a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, the computer instructions comprising:

obtaining characterization data describing driving behavior of the at least one logic gate, wherein the characterization data is obtained from a circuit-level model of the at least one logic gate and is in a form that approximates a current source, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance;

obtaining a model of the interconnect circuit;

deriving a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit, wherein the deriving of a sequence of crossing times comprises estimating a charge supplied by the at least one logic gate to the interconnect circuit on a piecewise basis at each of the successive voltage thresholds provided in the driving point voltage waveform, and determining a dynamic capacitance on a piecewise basis at each of the successive voltage thresholds from the estimated charges, wherein each crossing time is derived as a function of each determined dynamic capacitance and corresponding sequence of voltage thresholds; and

generating a voltage waveform by piecing together the derived sequence of crossing times and the corresponding sequence of voltage thresholds, wherein the generated voltage waveform is a piecewise linear waveform indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit.

7. The computer-readable storage device according to claim 6, wherein the obtaining of characterization data comprises instructions for accessing a library containing a plurality of tables representing the at least one logic gate loaded by various pure capacitive loads and excited by voltage waveforms of varying slew rates.

8. The computer-readable storage device according to claim 6, wherein the obtaining of the model of the interconnect circuit comprises instructions for obtaining a reduced ordered model of the interconnect that is represented in a pole/residue form.

9. The computer-readable storage device according to claim 6, further comprising instructions for using the generated voltage waveform to perform a timing analysis of the digital integrated circuit.

10. The computer-readable storage device according to claim 9, further comprising instructions for determining the timing of an entire path of the digital integrated circuit.

11. A computer system for performing a multiple voltage threshold timing analysis, comprising:

at least one processing unit;

memory operably associated with the at least one processing unit; and

a multiple voltage threshold timing analysis tool storable in memory and executable by the at least one processing unit for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit, the tool comprising;

a characterization data retrieving component configured to obtain characterization data describing driving behavior of the at least one logic gate, wherein the characterization data is obtained from a circuit-level model of the at least one logic gate and is in a form that approximates a current source, wherein the characterization data tabulates a driving point voltage waveform for the at least one logic gate as a function of slew of an input voltage ramp signal and load capacitance;

an interconnect circuit model retrieving component configured to obtain a model of the interconnect circuit; and

a multiple voltage threshold timing analysis component configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds from the characterization data of the at least one logic gate and the model of the interconnect circuit, wherein the deriving of a sequence of crossing times comprises estimating a charge supplied by the at least one logic gate to the interconnect circuit on a piecewise basis at each of the successive voltage thresholds provided in the driving point voltage waveform, and determining a dynamic capacitance on a piecewise basis at each of the successive voltage thresholds from the estimated charges, wherein each crossing time is derived as a function of each determined dynamic capacitance and corresponding sequence of voltage thresholds, and generate a voltage waveform by piecing together the derived sequence of crossing times and the corresponding sequence of voltage thresholds, wherein the generated voltage waveform is a piecewise linear waveform indicative of the driving point voltage of the at least one logic gate loaded by the interconnect circuit.

12. The system according to claim 11, wherein the characterization data retrieving component is configured to obtain the characterization data from a library containing a plurality of tables representing the at least one logic gate loaded by various pure capacitive loads and excited by voltage waveforms of varying slew rates.

13. The system according to claim 11, wherein the interconnect circuit model retrieving component is configured to obtain a reduced ordered model of the interconnect that is in a pole/residue form.

14. The system according to claim 11, wherein the multiple voltage threshold timing analysis component is further configured to use the generated voltage waveform to perform a timing analysis of the digital integrated circuit.

15. The system according to claim 14, wherein the multiple voltage threshold timing analysis component is further configured to determine the timing of an entire path within the digital integrated circuit.