Arrangement for energy conditioning

• US 8,023,241 B2
• Filed: 04/04/2011
• Issued: 09/20/2011
• Est. Priority Date: 04/08/1997
• Status: Expired due to Fees

• Current Assignee: X2Y Attenuators, LLC
• Original Assignee: X2Y Attenuators, LLC
• Inventors: Anthony, Anthony A., Anthony, William M.
• Primary Examiner(s): Jackson; Stephen W
• Application Number:
  US13/079,789
• Publication Number:
  US 20110192642A1
• Time in Patent Office: 169 Days
• Field of Search: 361/118
• US Class Current: 361/118
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 9/00 Screening of apparatus or components against electric or magnetic fields devices for absorbing radiation from an antenna H01Q17/00
• CPC Class Codes: H05K 9/0071 Active shielding
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49194 Assembling elongated conductors, e.g., splicing, etc.

Abstract

Circuit arrangement embodiments that use relative groupings of energy pathways that include shielding circuit arrangements that can sustain and condition electrically complementary energy confluences.

Claims

1. An arrangement of electrode portions comprising:

a first electrode having a first electrode portion, wherein said first electrode portion is supported by dielectric material;

a second electrode having a second electrode portion, wherein said second electrode portion is supported by said dielectric material;

a third electrode having a third electrode portion, wherein said third electrode portion is supported by said dielectric material;

a fourth electrode having a fourth electrode portion, wherein said fourth electrode portion is supported by said dielectric material;

a fifth electrode having a fifth electrode portion, wherein said fifth electrode portion is supported by said dielectric material;

wherein said second electrode and said fourth electrode are electrically insulated from each other;

wherein said first electrode, said third electrode, and said fifth electrode are electrically coupled to one another;

wherein said first electrode portion is stacked above said second electrode portion, said third electrode portion, said fourth electrode portion and said fifth electrode portion;

wherein said second electrode portion is stacked above said third electrode portion, said fourth electrode portion and said fifth electrode portion;

wherein said third electrode portion is stacked above said fourth electrode portion and said fifth electrode portion;

wherein said fourth electrode portion is stacked above said fifth electrode portion; and

wherein an area of said third electrode portion completely shields an area of said second electrode portion and an area of said fourth electrode portion from one another;

wherein said area of said second electrode portion is sandwiched between said first electrode portion and said third electrode portion;

wherein said area of said fourth electrode portion is sandwiched between said third electrode portion and said fifth electrode portion;

wherein said area of said second electrode portion and said area of said fourth electrode portion overlap one another;

wherein said arrangement is operable to provide attenuation of radiated electromagnetic emissions from energy propagating within said arrangement when said arrangement is energized; and

wherein said arrangement is operable to provide electrostatic shielding of energy propagating within said arrangement when said arrangement is energized.

2. The arrangement of claim 1, wherein said attenuation of radiated electromagnetic emissions from energy propagating within said arrangement and said electrostatic shielding of energy propagating within said arrangement occur simultaneously when said arrangement of electrode portions is energized.

3. The arrangement of claim 1, wherein said second electrode is operable for a first conductive connection;

and

wherein said fourth electrode is operable for a second conductive connection.

4. The arrangement of claim 1, wherein said second electrode is operable for a first conductive connection;

wherein said fourth electrode is operable for a second conductive connection; and

wherein said attenuation of radiated electromagnetic emissions from energy propagating within said arrangement and said electrostatic shielding of energy propagating within said arrangement occur simultaneously when said arrangement of electrode portions is energized.

5. The arrangement of claim 2, wherein said first electrode portion, said second electrode portion, said third electrode portion, said fourth electrode portion and said fifth electrode portion are each located below a surface of a substrate.

6. The arrangement of claim 3, wherein said first electrode portion, said second electrode portion, said third electrode portion, said fourth electrode portion and said fifth electrode portion are each located below a surface of a substrate.

7. The arrangement of claim 4, wherein said first electrode portion, said second electrode portion, said third electrode portion, said fourth electrode portion and said fifth electrode portion are each located below a surface of a substrate.

8. A method of making an arrangement of electrode portions, said method comprising:

providing a first electrode that has at least a first electrode portion supported by dielectric material;

providing a second electrode that has at least a second electrode portion supported by said dielectric material;

providing a third electrode that has at least a third electrode portion supported by said dielectric material;

providing a fourth electrode that has at least a fourth electrode portion supported by said dielectric material;

providing a fifth electrode that has at least a fifth electrode portion supported by said dielectric material;

insulating said second electrode and said fourth electrode from each other;

electrically connecting said first electrode, said third electrode, and said fifth electrode to one another;

insulating said first electrode, said third electrode and said fifth electrode from said second electrode and said fourth electrode;

stacking said fourth electrode portion above said fifth electrode portion;

stacking said third electrode portion above said fourth electrode portion;

stacking said second electrode portion above said third electrode portion;

stacking said first electrode portion above said second electrode portion; and

positioning said third electrode portion between an area of said second electrode portion and an area of said fourth electrode portion such that said area of said second electrode portion and said area of said fourth electrode portion are completely shielded from one another by said third electrode portion;

aligning at least a portion of a perimeter of said area of said second electrode portion to at least a portion of a perimeter of said area of said fourth electrode portion;

sandwiching said area of said second electrode portion between said first electrode portion and said third electrode portion;

sandwiching said area of said fourth electrode portion between said third electrode portion and said fifth electrode portion; and

positioning said first electrode portion, said second electrode portion, said third electrode portion, said fourth electrode portion and said fifth electrode portion below a surface of a substrate,

such that when said first electrode and said second electrode are energized, said arrangement simultaneously attenuates radiated electromagnetic emissions from energy propagating within said arrangement of electrode portions while at least said first electrode portion, said third electrode portion, said fifth electrode portion together provide electrostatic shielding of energy propagating within said arrangement.

9. The method of claim 8, wherein said method further comprises:

making said second electrode operable for a first conductive connection; and

making said fourth electrode operable for a second conductive connection.

10. The method of claim 9, wherein said method further comprises:

electrically connecting at least said second electrode to an integrated circuit.

11. A method of making electrode portions operable for simultaneous energy conditioning, said method comprising:

providing a first electrode having a first electrode portion;

providing a second electrode having a second electrode portion, wherein said second electrode is operable for a first conductive connection;

providing a third electrode having a third electrode portion;

providing a fourth electrode having a fourth electrode portion, wherein said fourth electrode is operable for a second conductive connection;

providing a fifth electrode having a fifth electrode portion; and

electrically connecting said first electrode, said third electrode, and said fifth electrode to one another; and

creating an arrangement of said electrode portions that includes;

positioning said first electrode portion above said second electrode portion;

positioning said second electrode portion above said third electrode portion;

positioning said third electrode portion above said fourth electrode portion;

positioning said fourth electrode portion above said fifth electrode portion;

and

insulating said second electrode and said fourth electrode from one another using a dielectric material, and insulating said first electrode, said third electrode and said fifth electrode from said second electrode and said fourth electrode using said dielectric material;

positioning said third electrode portion between an area of said second electrode portion and an area of said fourth electrode portion wherein said area of said second electrode portion and said area of said fourth electrode portion are superposed;

positioning said area of said second electrode portion between said first electrode portion and said third electrode portion;

positioning said area of said fourth electrode portion between said third electrode portion and said fifth electrode portion; and

positioning said arrangement below a surface of a substrate such that when both said second electrode and said fourth electrode are energized together, said arrangement causes attenuation of radiated electromagnetic emissions from energy propagating said area of said second electrode portion or said area of said fourth electrode portion, while said first electrode portion, said third electrode portion and said fifth electrode portion provide electrostatic shielding of energy propagating either said area of said second electrode portion or said area of said fourth electrode portion.

12. The method of claim 11, wherein when both said second electrode and said fourth electrode are energized, said arrangement causes attenuation of radiated electromagnetic emissions from energy propagating said area of said second electrode portion or said area of said fourth electrode portion and said first electrode portion, said third electrode portion and said fifth electrode portion provide electrostatic shielding of energy propagating either said area of said second electrode portion or said area of said fourth electrode portion, simultaneously.

13. The method of claim 11, further comprising:

providing a sixth electrode having a sixth electrode portion;

providing a seventh electrode having a seventh electrode portion;

positioning said first electrode portion on a first layer of said dielectric material;

positioning said second electrode portion and said sixth electrode portion on a second layer of said dielectric material;

positioning said third electrode portion on a third layer of said dielectric material;

positioning said fourth electrode portion and said seventh electrode portion on a fourth layer of dielectric material; and

positioning said fifth electrode portion on a fifth layer of dielectric material.

14. An arrangement for energy conditioning, comprising:

an upper electrode comprising a shielding upper electrode area;

a first electrode comprising a first shielded surface area, and wherein said first shielded surface area includes a first superposed area and a first non-superposed area, and wherein said first superposed area includes a top first superposed area and a bottom first superposed area;

a center electrode comprising a shielding center electrode area;

a second electrode comprising a second shielded surface area, and wherein said second shielded surface area includes a second superposed area and a second non-superposed area, and wherein said second superposed area includes a top second superposed area and a bottom second superposed area;

a lower electrode comprising a shielding lower electrode area;

wherein said shielding upper electrode area is electrically coupled to said shielding center electrode area, and wherein said shielding center electrode area is electrically coupled to said shielding lower electrode area, and wherein said shielding upper electrode area, said shielding center electrode area and said shielding lower electrode area are each electrically isolated from said first electrode and said second electrode, and wherein said first electrode and said second electrode are electrically isolated from each other;

wherein said top first superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by a first horizontal distance, and wherein said bottom first superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by said first horizontal distance;

wherein said bottom second superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by a second horizontal distance, and wherein said top second superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by said second horizontal distance; and

wherein said top first superposed area and said bottom first superposed area are superposed with one another, and wherein said top second superposed area and said bottom second superposed area are superposed with one another, and wherein said bottom first superposed area and said top second superposed area are arranged superposed with each other.

15. The arrangement for energy conditioning of claim 14, further comprising:

a dielectric; and

wherein said shielding upper electrode area comprises a top upper superposed surface area, a bottom upper superposed surface area, a top upper non-superposed surface area and a bottom upper non-superposed surface area;

wherein said shielding center electrode area comprises a top center superposed surface area, a bottom center superposed surface area, a top center non-superposed surface area and a bottom center non-superposed surface area;

wherein said shielding lower electrode area comprises a top lower superposed surface area, a bottom lower superposed surface area, a top lower non-superposed surface area and a bottom lower non-superposed surface area; and

wherein said top upper superposed surface area and said bottom upper superposed surface area are superposed with one another, and wherein said top center superposed surface area and said bottom center superposed surface area are superposed with one another, and wherein said top lower superposed surface area and said bottom lower superposed surface area are superposed with one another.

16. The arrangement for energy conditioning of claim 15, further comprising:

a first layer of said dielectric containing a first dielectric layer section that includes a top surface area and a bottom surface area that are the same size;

a second layer of said dielectric containing a second dielectric layer section that includes a top surface area and a bottom surface area that are the same size;

a third layer of said dielectric containing a third dielectric layer section that includes a top surface area and a bottom surface area that are the same size;

a fourth layer of said dielectric containing a fourth dielectric layer section includes a top surface area and a bottom surface area that are the same size;

wherein said bottom upper superposed surface area is spaced directly apart from said top first superposed area by said first dielectric layer section;

wherein said bottom first superposed area is spaced directly apart from said top center superposed surface area by said second dielectric layer section;

wherein said bottom center superposed surface area is spaced directly apart from said top second superposed area by said third dielectric layer section;

wherein said bottom second superposed area is spaced directly apart from said top lower superposed surface area by said fourth dielectric layer section; and

wherein the size of said top upper superposed surface area, the size of said bottom upper superposed surface area, the size of said top surface area of said first dielectric layer section, the size of said bottom surface area of said first dielectric layer section, the size of said top first superposed area, the size of said bottom first superposed area, the size of said top surface area of said second dielectric layer section, the size of said bottom surface area of said second dielectric layer section, the size of said top center superposed surface area, the size of said bottom center superposed surface area, the size of said top surface area of said third dielectric layer section, the size of said bottom surface area of said third dielectric layer section, the size of said top second superposed area, the size of said bottom second superposed area, the size of said top surface area of said fourth dielectric layer section, the size of said bottom surface area of said fourth dielectric layer section, the size of said top lower superposed surface area and the size of said bottom lower superposed surface area are each approximately the same size.

17. The arrangement for energy conditioning of claim 16, wherein a stacked superposed arrangement consisting essentially of said bottom upper superposed surface area, both said surface areas of said first dielectric layer section, said top first superposed area, said bottom first superposed area, both said surface areas of said second dielectric layer section, said top center superposed surface area, said bottom center superposed surface area, both said surface areas of said third dielectric layer section, said top second superposed area, said bottom second superposed area, both said surface areas of said fourth dielectric layer section and said top lower superposed surface area defines a three-dimensional section within said arrangement for energy conditioning.

18. The arrangement for energy conditioning of claim 15, further comprising:

a first layer of said dielectric containing a first dielectric layer section that includes a top surface area and a bottom surface area that are the same size;

a second layer of said dielectric containing a second dielectric layer section that includes a top surface area and a bottom surface area that are the same size;

a third layer of said dielectric containing a third dielectric layer section that includes a top surface area and a bottom surface area that are the same size;

a fourth layer of said dielectric containing a fourth dielectric layer section includes a top surface area and a bottom surface area that are the same size;

wherein said first dielectric layer section spaces apart said bottom upper superposed surface from said top first superposed area;

wherein said second dielectric layer section spaces apart said bottom first superposed area from said top center superposed surface area;

wherein said third dielectric layer section spaces apart said bottom center superposed from said top second superposed area;

wherein said fourth dielectric layer section spaces apart said bottom second superposed area from said top lower superposed surface area;

wherein the thickness of said second dielectric layer section is approximately the same as the thickness of said third dielectric layer section; and

wherein the size of said top upper superposed surface area, the size of said bottom upper superposed surface area, the size of said top surface area of said first dielectric layer section, the size of said bottom surface area of said first dielectric layer section, the size of said top first superposed area, the size of said bottom first superposed area, the size of said top surface area of said second dielectric layer section, the size of said bottom surface area of said second dielectric layer section, the size of said top center superposed surface area, the size of said bottom center superposed surface area, the size of said top surface area of said third dielectric layer section, the size of said bottom surface area of said third dielectric layer section, the size of said top second superposed area, the size of said bottom second superposed area, the size of said top surface area of said fourth dielectric layer section, the size of said bottom surface area of said fourth dielectric layer section, the size of said top lower superposed surface area and the size of said bottom lower superposed surface area are each approximately the same size.

19. The arrangement for energy conditioning of claim 18, wherein said top upper superposed surface area, said bottom upper superposed surface area, both said surface areas of said first dielectric layer section, said top first superposed area, said bottom first superposed area, both said surface areas of said second dielectric layer section, said top center superposed surface area, said bottom center superposed surface area, both said surface areas of said third dielectric layer section, said top second superposed area, said bottom second superposed area, both said surface areas of said fourth dielectric layer section and said top lower superposed surface area and said bottom lower superposed surface area are stacked superposed with one another and form a first superposed arrangement.

20. The arrangement for energy conditioning of claim 19, wherein the length of said first perimeter edge portion of said bottom first superposed area and the length of said first perimeter edge portion of said top second superposed area are approximately the same such that said first perimeter edge portion of said bottom first superposed area and said first perimeter edge portion of said top second superposed area are superposed with one another in a first superposed perimeter edge portion arrangement;

and

wherein the length of said second perimeter edge portion of said bottom first superposed area and the length of said second perimeter edge portion of said top second superposed area are approximately the same such that said second perimeter edge portion of said bottom first superposed area and said second perimeter edge portion of said top second superposed area are superposed with one another in a second superposed perimeter edge portion arrangement.

21. The arrangement for energy conditioning of claim 20, further comprising:

a top layer of said dielectric and a bottom layer of said dielectric,

wherein said top layer of said dielectric is directly above said shielding upper electrode area; and

wherein said bottom layer of said dielectric is directly below said shielding lower electrode area.

22. The arrangement for energy conditioning of claim 21, wherein said first electrode is a first bypass electrode;

and

wherein said second electrode is a second bypass electrode.

23. The arrangement for energy conditioning of claim 22, further comprising:

an integrated circuit chip;

a portion of said first electrode electrically coupled to a first portion of said integrated circuit chip;

a portion of said second electrode electrically coupled to a second portion of said integrated circuit chip;

a symmetrical bypass electrode arrangement within said first superposed arrangement that includes said top upper superposed surface area, said bottom upper superposed surface area, said top first superposed area, said bottom first superposed area, said top center superposed surface area, said bottom center superposed surface area, said top second superposed area, said bottom second superposed area, said top lower superposed surface area and said bottom lower superposed surface area; and

wherein said symmetrical bypass electrode arrangement is operable for at least filtering energy transmissions when said integrated circuit chip is energized.

24. The arrangement for energy conditioning of claim 20, further comprising:

a substrate including a top substrate area and a bottom substrate area,

wherein said first superposed arrangement is located between said top substrate area and said bottom substrate area.

25. The arrangement for energy conditioning of claim 24, wherein said first electrode is operable as a feed-thru electrode when said first electrode is energized;

and

wherein said second electrode is operable as a feed-thru electrode when said second electrode is energized.

26. The arrangement for energy conditioning of claim 25, wherein said arrangement for energy conditioning is operable for at least shielding an energy transmission within said first superposed arrangement when at least said first electrode is energized.

27. The arrangement for energy conditioning of claim 17, further comprising:

a substrate including a top substrate area and a bottom substrate area, and wherein said top substrate area comprises a top substrate area surface; and

wherein said bottom substrate area comprises a bottom substrate area surface.

28. The arrangement for energy conditioning of claim 27, wherein the length of said first perimeter edge portion of said bottom first superposed area and the length of said first perimeter edge portion of said top second superposed area are approximately the same such that said first perimeter edge portion of said bottom first superposed area and said first perimeter edge portion of said top second superposed area are superposed with one another in a first superposed perimeter edge portion arrangement;

and

wherein the length of said second perimeter edge portion of said bottom first superposed area and the length of said second perimeter edge portion of said top second superposed area are approximately the same such that said second perimeter edge portion of said bottom first superposed area and said second perimeter edge portion of said top second superposed area are superposed with one another in a second superposed perimeter edge portion arrangement.

29. The arrangement for energy conditioning of claim 28, further comprising:

an integrated circuit chip;

a third electrode comprising a third shielded surface area, and wherein said third shielded surface area includes a third superposed area and a third non-superposed area, and wherein said third superposed area includes a top third superposed area and a bottom third superposed area;

a fourth electrode comprising a fourth shielded surface area, and wherein said fourth shielded surface area includes a fourth superposed area and a fourth non-superposed area, and wherein said fourth superposed area includes a top fourth superposed area and a bottom fourth superposed area;

wherein said top third superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by a third horizontal distance;

wherein said bottom third superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by said third horizontal distance;

wherein said bottom fourth superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by a fourth horizontal distance;

wherein said top fourth superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by said fourth horizontal distance;

wherein said top third superposed area and said bottom third superposed area are superposed with one another, and wherein said top fourth superposed area and said bottom fourth superposed area are superposed with one another; and

wherein said bottom third superposed area and said top fourth superposed area are superposed with each other.

30. The arrangement for energy conditioning of claim 29, wherein said top first superposed area and said top third superposed area are co-planar with one another;

wherein said bottom first superposed area and said bottom third superposed area are co-planar with one another;

wherein said top second superposed area and said top fourth superposed area are co-planar with one another; and

wherein said bottom second superposed area and said bottom fourth superposed area are co-planar with one another.

31. The arrangement for energy conditioning of claim 30, wherein the length of said first perimeter edge portion of said bottom third superposed area and the length of said first perimeter edge portion of said top second superposed area are approximately the same such that said first perimeter edge portion of said bottom third superposed area and said first perimeter edge portion of said top second superposed area are superposed with one another in a third superposed perimeter edge portion arrangement;

and

wherein the length of said second perimeter edge portion of said bottom third superposed area and the length of said second perimeter edge portion of said top fourth superposed area are approximately the same such that said second perimeter edge portion of said bottom third superposed area and said second perimeter edge portion of said top fourth superposed area are superposed with one another in a fourth superposed perimeter edge portion arrangement;

wherein the boundary of said three-dimensional section within said arrangement for energy conditioning includes said first superposed perimeter edge portion arrangement and said second superposed perimeter edge portion arrangement; and

wherein said stacked superposed arrangement, said first superposed perimeter edge portion arrangement, said second superposed perimeter edge portion arrangement, said third superposed perimeter edge portion arrangement and said fourth superposed perimeter edge portion arrangement are within said substrate.

32. The arrangement for energy conditioning of claim 31, wherein a portion of said first electrode is electrically coupled to a first portion of said integrated circuit chip;

and

wherein a portion of said second electrode is electrically coupled to a second portion of said integrated circuit chip;

wherein a portion of said third electrode is electrically coupled to a third portion of said integrated circuit chip; and

wherein a portion of said fourth electrode is electrically coupled to a fourth portion of said integrated circuit chip.

33. The arrangement for energy conditioning of claim 32, wherein said first electrode is a first feed-thru electrode;

wherein said second electrode is a second feed-thru electrode;

wherein said third electrode is a third feed-thru electrode; and

wherein said fourth electrode is a fourth feed-thru electrode.

34. The arrangement for energy conditioning of claim 33, wherein said stacked superposed arrangement, said first superposed perimeter edge portion arrangement, said second superposed perimeter edge portion arrangement, said third superposed perimeter edge portion arrangement and said fourth superposed perimeter edge portion arrangement are located between said top substrate area surface and said bottom substrate area surface.

35. The arrangement for energy conditioning of claim 33, wherein portions of said three-dimensional section within said arrangement for energy conditioning are simultaneously operable for:

(a) a first capacitance developed when said integrated circuit chip is energized;

(b) a second capacitance developed when said integrated circuit chip is energized; and

(c) electrostatic shielding of energy when said integrated circuit chip is energized.

36. The arrangement for energy conditioning of claim 34, wherein the thickness of said second dielectric layer section is approximately the same as the thickness of said third dielectric layer section;

and

wherein the capacitance value of said first capacitance is approximately the same as the capacitance value of said second capacitance when said integrated circuit chip is energized.

37. The arrangement for energy conditioning of claim 16, further comprising:

an integrated circuit chip;

a substrate including a top substrate area and a bottom substrate area, and wherein said integrated circuit chip is coupled to said substrate;

a third electrode comprising a third shielded surface area, and wherein said third shielded surface area includes a third superposed area and a third non-superposed area, and wherein said third superposed area includes a top third superposed area and a bottom third superposed area;

a fourth electrode comprising a fourth shielded surface area, and wherein said fourth shielded surface area includes a fourth superposed area and a fourth non-superposed area, and wherein said fourth superposed area includes a top fourth superposed area and a bottom fourth superposed area;

wherein said top third superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by a third horizontal distance;

wherein said bottom third superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by said third horizontal distance;

wherein said bottom fourth superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by a fourth horizontal distance;

wherein said top fourth superposed area includes at least a first perimeter edge portion and a second perimeter edge portion that are spaced apart from one another by said fourth horizontal distance;

wherein said top first superposed area and said top third superposed area are co-planar with one another, and wherein said bottom first superposed area and said bottom third superposed area are co-planar with one another, and wherein said top second superposed area and said top fourth superposed area are co-planar with one another, and wherein said bottom second superposed area and said bottom fourth superposed area are co-planar with one another;

wherein a portion of said first electrode is electrically coupled to a first portion of said integrated circuit chip;

wherein a portion of said second electrode is electrically coupled to a second portion of said integrated circuit chip;

wherein a portion of said third electrode is electrically coupled to a third portion of said integrated circuit chip;

wherein a portion of said fourth electrode is electrically coupled to a fourth portion of said integrated circuit chip;

wherein the length of said first perimeter edge portion of said bottom first superposed area and the length of said first perimeter edge portion of said top second superposed area are approximately the same such that said first perimeter edge portion of said bottom first superposed area and said first perimeter edge portion of said top second superposed area are superposed with one another in a first superposed perimeter edge portion arrangement;

wherein the length of said second perimeter edge portion of said bottom first superposed area and the length of said second perimeter edge portion of said top second superposed area are approximately the same such that said second perimeter edge portion of said bottom first superposed area and said second perimeter edge portion of said top second superposed area are superposed with one another in a second superposed perimeter edge portion arrangement;

wherein the length of said first perimeter edge portion of said bottom third superposed area and the length of said first perimeter edge portion of said top second superposed area are approximately the same such that said first perimeter edge portion of said bottom third superposed area and said first perimeter edge portion of said top second superposed area are superposed with one another in a third superposed perimeter edge portion arrangement;

wherein the length of said second perimeter edge portion of said bottom third superposed area and the length of said second perimeter edge portion of said top fourth superposed area are approximately the same such that said second perimeter edge portion of said bottom third superposed area and said second perimeter edge portion of said top fourth superposed area are superposed with one another in a fourth superposed perimeter edge portion arrangement;

wherein said top upper superposed surface area, said bottom upper superposed surface area, both said surface areas of said first dielectric layer section, said top first superposed area, said bottom first superposed area, both said surface areas of said second dielectric layer section, said top center superposed surface area, said bottom center superposed surface area, both said surface areas of said third dielectric layer section, said top second superposed area, said bottom second superposed area, both said surface areas of said fourth dielectric layer section and said top lower superposed surface area and said bottom lower superposed surface area are stacked superposed with one another and form a first superposed arrangement; and

wherein said first superposed arrangement, said first superposed perimeter edge portion arrangement, said second superposed perimeter edge portion arrangement, said third superposed perimeter edge portion arrangement and said fourth superposed perimeter edge portion arrangement are between said top substrate area and said bottom substrate area.

38. The arrangement for energy conditioning of claim 37, wherein said third electrode and said fourth electrode are electrically isolated from each other;

wherein said first electrode and said second electrode are electrically isolated from said third electrode and said fourth electrode;

wherein said first electrode is a first feed-thru electrode;

wherein said second electrode is a second feed-thru electrode;

wherein said third electrode is a third feed-thru electrode; and

wherein said fourth electrode is a fourth feed-thru electrode.

39. The arrangement for energy conditioning of claim 38, further comprising:

a second upper electrode comprising a second shielding upper electrode area;

a second center electrode comprising a second shielding center electrode area;

a second lower electrode comprising a second shielding lower electrode area;

wherein said second shielding upper electrode area comprises a top superposed surface area, a bottom superposed surface area, a top non-superposed surface area and a bottom non-superposed surface area;

wherein said second shielding center electrode area comprises a top superposed surface area, a bottom superposed surface area, a top non-superposed surface area and a bottom non-superposed surface area;

wherein said second shielding lower electrode area comprises a top superposed surface area, a bottom superposed surface area, a top non-superposed surface area and a bottom non-superposed surface area; and

wherein said top superposed surface area and said bottom superposed surface area of said second shielding upper electrode area are superposed with one another, and wherein said top superposed surface area and said bottom superposed surface area of said second shielding center electrode area are superposed with one another, and wherein said top superposed surface area and said bottom superposed surface area of said second shielding lower electrode area are superposed with one another;

wherein said second shielding upper electrode area is electrically coupled to said second shielding center electrode area, and wherein said second shielding center electrode area is electrically coupled to said second shielding lower electrode area; and

wherein said second shielding upper electrode area, said second shielding center electrode area and said second shielding lower electrode area are electrically isolated from said first electrode, said second electrode, said third electrode and said fourth electrode; and

wherein said second shielding upper electrode area, said second shielding center electrode area and said second shielding lower electrode area are below said shielding lower electrode area.

40. The arrangement for energy conditioning of claim 39, wherein said shielding lower electrode area and said second shielding upper electrode area are conductively coupled at least to one another.

41. The arrangement for energy conditioning of claim 40, wherein the thickness of said second dielectric layer section is approximately the same as the thickness of said third dielectric layer section;

and

wherein said second shielding upper electrode area, said second shielding center electrode area and said second shielding lower electrode area are between said top substrate area and said bottom substrate area.

42. The arrangement for energy conditioning of claim 41, wherein said arrangement for energy conditioning is at least operable for simultaneously shielding two energy transmissions that are passing through said first superposed arrangement when said integrated circuit chip is energized.