Method and apparatus for code optimization

• US 8,024,716 B2
• Filed: 07/26/2005
• Issued: 09/20/2011
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Peltier, Mikael, Cabillic, Gilbert, Lesot, Jean-Philippe
• Primary Examiner(s): Zhen; Li
• Assistant Examiner(s): COYER, RYAN D
• Application Number:
  US11/189,211
• Publication Number:
  US 20060026574A1
• Time in Patent Office: 2,247 Days
• Field of Search: 717/146, 717/148, 717/158, 717151-153
• US Class Current: 717/148
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/6012 of operating mode, e.g. cache mode or local memory mode
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system comprising a compiler that compiles source-level code to generate an intermediate-level instruction comprising a predetermined component. The intermediate-level instruction is an at least partially optimized version of the source-level code. Execution of the predetermined component triggers the execution of a series of instructions that, when executed, generates previously-unavailable data that is used to re-generate the intermediate-level instruction. The re-generated intermediate-level instruction has a length less than or equal to that of the intermediate-level instruction.

Claims

1. A system, comprising:

a processor; and

a compiler configured to execute on the processor to compile Java source code for execution on the processor, wherein the compiler generates a sing intermediate instruction optimizable to a single native instruction at runtime and replaces the single intermediate instruction with a single native rewrite instruction comprising a rewrite operation code,

wherein execution of the single native rewrite instruction by the processor rewrites the single native rewrite instruction into the single native instruction, and

wherein the single intermediate instruction comprises an operation code of a first instruction set type of the processor, and the single native rewrite instruction is an instruction in a second instruction set type of the processor.

2. The system of claim 1, wherein execution of the single native rewrite instruction comprises selection of a series of instructions based on the rewrite operation code, wherein execution of the series of instructions rewrites the single native rewrite instruction into the single native instruction.

3. The system of claim 2, wherein the rewrite operation code corresponds to an entry in a data structure used by decode logic of the processor, the entry comprising a reference to a storage address of the series of instructions.

4. The system of claim 2, further comprising a virtual machine coupled to the processor, wherein the series of instructions is generated by the virtual machine and stored in memory.

5. The system of claim 1, wherein the single native rewrite instruction further comprises a parameter of the single intermediate instruction, a pointer to a computation function configured to transform the parameter into at least one parameter of the single native instruction, and a pointer to a rewrite function configured to rewrite the single native rewrite instruction into the single native instruction using the at least one parameter.

6. The system of claim 5, wherein the single native rewrite instruction further comprises register numbers of source and destination registers of the single native instruction and wherein the rewrite function is further configured to rewrite the single native rewrite instruction using the register numbers.

7. The system of claim 1, wherein the single native instruction has a length less than or equal to that of the single native rewrite instruction.

8. A processor, comprising:

a fetch logic configured to fetch from storage compiled Java code comprising a single native rewrite instruction that replaced a single intermediate instruction optimizable to a single native instruction at runtime during compilation, wherein the single native rewrite instruction comprises a rewrite operation code;

a decade logic coupled to the fetch logic and configured to decode the compiled code,

wherein, upon decoding the rewrite operation code, the decode logic causes execution of the single native rewrite instruction by the processor to rewrite the single native rewrite instruction into the single native instruction, and

wherein, the single intermediate instruction comprises an operation code of a first instruction set type of the processor, and the single native rewrite instruction is an instruction in a second instruction set type of the processor.

9. The processor of claim 8, further comprising a vector table having an entry corresponding to the single native rewrite instruction and comprising a reference to a location of a group of instructions in a memory, and wherein the decode logic causes execution by using the rewrite operation code to locate the entry and executing the group of instructions.

10. The processor of claim 9, wherein a virtual machine executing on the processor is configured to generate the group of instructions and store the group of instructions in the memory.

11. The processor of claim 8, wherein the single native rewrite instruction further comprises a parameter of the single intermediate instruction, a pointer to a computation function configured to transform the parameter into at least one parameter of the single native instruction, and a pointer to a rewrite function configured to rewrite the single native rewrite instruction into the single native instruction using the at least one parameter.

12. The processor of claim 11, wherein the single native rewrite instruction further comprises register numbers of source and destination registers of the single native instruction and wherein the rewrite function is further configured to rewrite the single native rewrite instruction using the register numbers.

13. A computer-implemented method, comprising:

compiling source-level Java code to generate a single intermediate instruction, wherein the single intermediate instruction is optimizable to a single native instruction at runtime; and

replacing the single intermediate instruction with a single native rewrite instruction comprising a rewrite operation code, wherein execution of the single native rewrite instruction by a processor rewrites the single native rewrite instruction into the single native instruction, and wherein the single intermediate instruction comprises an operation code of a first instruction set type of the processor, and the single native rewrite instruction is an instruction in a second instruction set type of the processor.

14. The method of claim 13, wherein the single native rewrite instruction further comprises a parameter of the single intermediate instruction, a pointer to a computation function configured to transform the parameter into at least one parameter of the single native instruction, and a pointer to a rewrite function configured to rewrite the single native rewrite instruction into the single native instruction using the at least one parameter.

15. The method of claim 13, wherein the single native instruction has a length less than or equal to that of the single native rewrite instruction.

16. A computer-implemented method, comprising:

decoding a single native rewrite instruction comprised in compiled Java code, wherein the single native rewrite instruction comprises a rewrite operation code and wherein, during compilation, the single native rewrite instruction replaced a single intermediate instruction optimizable to a single native instruction at runtime; and

responsive to the decoding, executing the single native rewrite instruction on a processor to rewrite the single native rewrite instruction into the single native instruction, wherein the single intermediate instruction comprises an operation code of a first instruction set type of the processor, and the single native rewrite instruction is an instruction in a second instruction set type of the processor.

17. The computer-implemented method of claim 16, wherein executing the single native rewrite instruction comprises selecting a sequence of instructions using the rewrite operation code to locate an entry in a vector table, wherein the entry comprises a reference to the sequence of instructions.

18. The computer-implemented method of claim 16, wherein executing the single native rewrite instruction comprises executing a computation function referenced in the single native rewrite instruction to transform a parameter of the single intermediate instruction comprised in the single native rewrite instruction into at least one parameter of the single native instruction.

19. The computer-implemented method of claim 16, wherein executing the single native rewrite instruction comprises executing a rewrite function referenced in the single native rewrite instruction to rewrite the single native rewrite instruction into the single native instruction.