Method and apparatus for ensuring fairness and forward progress when executing multiple threads of execution
First Claim
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1. An apparatus comprising:
- logic circuitry to determine fairness of execution of a first thread relative to execution of a second thread based on a single value stored in a fairness counter, wherein the fairness counter is to be incremented in response to execution of one of the first thread or second thread and is to be decremented in response to execution of another one of the first thread or second thread, wherein the fairness counter is to be incremented or decremented in response to an execution event corresponding to the first thread or second thread, the event comprising;
processor cycles, weighted processor cycles, or weighted instruction counts,logic circuitry to identify a next thread for execution based on the determined fairness and an execution information signal that indicates information about currently executing threads, wherein the logic circuitry to identify the next thread is to cause generation of a next thread signal to cause a processor to execute the next thread; and
logic to determine forward progress of a plurality of executing threads based on values stored in respective forward progress counters and a switch stimulus type from a plurality of switch stimulus types, wherein a value of a forward progress counter is to indicate whether to permit a voluntary switching out of a corresponding thread, and wherein the first thread and the second thread are distinct.
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Abstract
A system and method for determine which threads to execute at a given time in a multi-threaded computer system. A thread prioritizer determines execution fairness between pairs of potentially executing threads. A switch enabler determines forward progress of each executing thread. The resulting indicators from the thread prioritizer and switch enabler may aid in the determination of whether or not to switch a particular potentially executing thread into execution resources.
67 Citations
40 Claims
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1. An apparatus comprising:
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logic circuitry to determine fairness of execution of a first thread relative to execution of a second thread based on a single value stored in a fairness counter, wherein the fairness counter is to be incremented in response to execution of one of the first thread or second thread and is to be decremented in response to execution of another one of the first thread or second thread, wherein the fairness counter is to be incremented or decremented in response to an execution event corresponding to the first thread or second thread, the event comprising;
processor cycles, weighted processor cycles, or weighted instruction counts,logic circuitry to identify a next thread for execution based on the determined fairness and an execution information signal that indicates information about currently executing threads, wherein the logic circuitry to identify the next thread is to cause generation of a next thread signal to cause a processor to execute the next thread; and logic to determine forward progress of a plurality of executing threads based on values stored in respective forward progress counters and a switch stimulus type from a plurality of switch stimulus types, wherein a value of a forward progress counter is to indicate whether to permit a voluntary switching out of a corresponding thread, and wherein the first thread and the second thread are distinct. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method comprising:
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determining fairness of execution of a first thread relative to execution of a second thread based on a single value stored in a fairness counter, wherein the fairness counter is to be incremented in response to execution of one of the first thread or second thread and is to be decremented in response to execution of another one of the first thread or second thread, wherein the fairness counter is to be incremented or decremented in response to an execution event corresponding to the first thread or second thread, the event comprising;
processor cycles, weighted processor cycles, or weighted instruction counts;identifying a next thread for execution based on the determined fairness and an execution information signal that indicates information about currently executing threads; causing generation of a next thread signal to cause a processor to execute the next thread; and determining forward progress of a plurality of executing threads based on values stored in respective forward progress counters and a switch stimulus type from a plurality of switch stimulus types, wherein a value of a forward progress counter is to indicate whether to permit a voluntary switching out of a corresponding thread, and wherein the first thread and the second thread are distinct. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25)
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26. A non-transitory computer readable media containing a program executable by a machine to perform operations that result in:
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determining fairness of execution of a first thread relative to execution of a second thread based on a single value stored in a fairness counter, wherein the fairness counter is to be incremented in response to execution of one of the first thread or second thread and is to be decremented in response to execution of another one of the first thread or second thread, wherein the fairness counter is to be incremented or decremented in response to an execution event corresponding to the first thread or second thread, the event comprising;
processor cycles, weighted processor cycles, or weighted instruction counts;identifying a next thread for execution based on the determined fairness and an execution information signal that indicates information about currently executing threads; causing generation of a next thread signal to cause a processor to execute the next thread; and determining forward progress of a plurality of executing threads based on values stored in respective forward progress counters and a switch stimulus type from a plurality of switch stimulus types, wherein a value of a forward progress counter is to indicate whether to permit a voluntary switching out of a corresponding thread, and wherein the first thread and the second thread are distinct. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34)
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35. A system comprising:
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a processor including logic to determine fairness of execution of a first thread relative to execution of a second thread based on a single value stored in a fairness counter, wherein the fairness counter is to be incremented in response to execution of one of the first thread or second thread and is to be decremented in response to execution of another one of the first thread or second thread, and logic to identify a next thread for execution based on the determined fairness and an execution information signal that indicates information about currently executing threads, wherein the logic circuitry to identify the next thread is to cause generation of a next thread signal to cause the processor to execute the next thread, wherein the fairness counter is to be incremented or decremented in response to an execution event corresponding to the first thread or second thread, the event comprising;
processor cycles, weighted processor cycles, or weighted instruction counts;a fixed disk; and logic to determine forward progress of a plurality of executing threads based on values stored in respective forward progress counters and a switch stimulus type from a plurality of switch stimulus types, wherein a value of a forward progress counter is to indicate whether to permit a voluntary switching out of a corresponding thread, and wherein the first thread and the second thread are distinct. - View Dependent Claims (36, 37, 38, 39, 40)
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Specification