Integrating a first contact structure in a gate last process

• US 8,035,165 B2
• Filed: 12/22/2008
• Issued: 10/11/2011
• Est. Priority Date: 08/26/2008
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Ming-Yuan, Thei, Kong-Beng, Chuang, Harry, Liang, Mong-Song, Yeh, Chiung-Han
• Primary Examiner(s): Pham; Hoai V
• Application Number:
  US12/341,891
• Publication Number:
  US 20100052075A1
• Time in Patent Office: 1,023 Days
• Field of Search: 257/369, 257/388, 257/406, 257/407, 257/412, 257/758, 257/E27.062, 257/E27.06
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence

Abstract

A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a transistor formed in the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric;

a dual first contact formed on the substrate, the dual first contact including;

a first contact feature;

a second contact feature overlying the first contact feature; and

a metal barrier layer formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature; and

a dummy contact plug formed in the substrate adjacent the transistor and substantially coplanar with the second contact feature.

2. The semiconductor device of claim 1, wherein the first contact feature and the second contact feature are each one of copper (Cu) and tungsten (W).

3. The semiconductor device of claim 1, wherein the first contact feature has substantially a different width as the second contact feature.

4. The semiconductor device of claim 1, wherein the high-k gate dielectric includes one of HfO₂, HfZrO, and HfSiO₄.

5. The semiconductor device of claim 1, wherein the high-k gate dielectric is a multi-layer structure including one of HfO₂/SiO₂ and HfO₂/SiON.

6. The semiconductor device of claim 1, wherein the transistor further includes a capping layer formed on the high-k gate dielectric, the capping layer including one of Al₂O₃, La₂O₃, and LaSiO.

7. The semiconductor device of claim 1, wherein the transistor further includes a capping layer formed on the high-k gate dielectric, the capping layer having a multi-layer structure including one of La₂O₃/Si and La₂O₃/Al₂O₃.

8. The semiconductor device of claim 1, wherein the metal gate includes one of Al, W, Cu, WN, TiN, and combinations thereof.

9. The semiconductor device of claim 1, wherein the transistor includes a doped region, wherein the first contact feature is coupled to the doped region via a silicide feature.

10. A semiconductor device, comprising:

a semiconductor substrate having a first region and a second region, wherein the second region includes a pattern density that is substantially less than a pattern density of the first region;

at least two transistors formed in the first region, the at least two transistors each having a metal gate and high-k gate dielectric; and

a dual contact structure formed in the first region between the at least two transistors, the dual contact structure including;

a first contact plug, the first contact plug having a surface that is co-planar with a surface of the metal gate; and

a second contact plug coupled to the surface of the first contact plug; and

a dummy contact plug disposed in the second region, the dummy contact plug being co-planar with the first contact plug.

11. The semiconductor device of claim 10, further comprising a first metal layer of an interconnect structure, wherein the second contact plug is coupled to the first metal layer.

12. The semiconductor device of claim 10, wherein the first contact plug, second contact plug, and dummy contact plug are each one of copper (Cu) and tungsten (W).

13. The semiconductor device of claim 10, wherein the dual contact structure further includes a metal barrier layer formed on the sidewalls and bottom of the second contact plug, the metal barrier layer coupling the first contact plug to the second contact plug.

14. The semiconductor device of claim 10, wherein the dual contact structure includes a barrier metal layer formed on the sidewalls and bottom of the second contact plug, the barrier metal layer directly contacting the surface of the first contact plug.

15. A semiconductor device comprising:

a semiconductor substrate;

a transistor having a gate structure including a metal gate electrode and high-k gate dielectric disposed over the substrate; and

a contact structure disposed over the substrate, the contact structure including;

a first contact portion having a surface that is substantially co-planar with a surface of the metal gate electrode;

a second contact portion overlying the first contact portion;

a metal barrier layer disposed between the first contact portion and the second contact portion such that the metal barrier layer connects the first contact portion to the second contact portion and

a dummy contact plug disposed in the substrate adjacent the transistor and substantially coplanar with the first contact.

16. The semiconductor device of claim 15, wherein the first and second contact portions each includes one of copper (Cu) and tungsten (W);

and

wherein the metal barrier layer includes TiN.

17. The semiconductor device of claim 15, wherein the metal barrier layer is further disposed on sidewalls of the second contact portion.

18. The semiconductor device of claim 15, wherein the transistor further includes a doped region, wherein the first contact portion is coupled to the doped region via a silicide feature.

19. The semiconductor device of claim 15, wherein the first contact portion has substantially a different width as the second contact portion.

20. The semiconductor device of claim 15, wherein the substrate has a first region and a second region, the first region having a pattern density that is substantially greater than a pattern density of the second region, and

wherein the transistor is disposed in the first region and the dummy contact plug is disposed in the second region.