CMOS time delay integration sensor for X-ray imaging applications

• US 8,039,811 B1
• Filed: 11/30/2010
• Issued: 10/18/2011
• Est. Priority Date: 12/04/2009
• Status: Active Grant

• Current Assignee: X-Scan Imaging Corporation
• Original Assignee: X-Scan Imaging Corporation
• Inventors: Li, Shizu, Wang, Chinlee
• Primary Examiner(s): Porta; David P.
• Assistant Examiner(s): Kim; Kiho
• Application Number:
  US12/927,961
• Time in Patent Office: 322 Days
• Field of Search: 25037001-37015, 250/208.1, 250/214.R, 250/214.A, 378/98.8, 348/295, 348/308, 348/294, 348302-307, 348/243, 348/241
• US Class Current: 250/370.14
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/768 for time delay and integration [TDI]
• CPC Class Codes: H04N 5/32 Transforming X-rays cameras or camera modules for generating image signals from X-rays H04N23/30; circuitry of SSIS for transforming X-rays into image signals H04N25/30

Abstract

A CMOS TDI image sensor consists of M pixels where each pixel is formed by a column of N TDI stages. Each TDI stage contains a photodiode that collects photo-charge and a pre-amplifier that proportionally converts the photo-charge to a voltage. Each TDI stage also has a set of capacitors, amplifiers, and switches for storage of the integrated signal voltages, where Correlated Double Sampling (CDS) technique (true or pseudo) maintains both photo-signal and reset voltages simultaneously. The CDS signal voltages can be passed from one TDI stage to the next TDI stage along a column for summing. The CDS signal voltages of the last TDI stages of M pixels are read out with a differential amplifier. This CMOS TDI structure is especially advantageous for implementing X-ray scanning detector systems requiring large pixel sizes and signal processing circuitry that is physically separated from the photodiode array for X-ray shielding.

Claims

1. A CMOS TDI detector stage comprising:

an integrating and summing amplifier having an integrating input terminal, a summing input terminal which may be joined to or may be separated from said integrating input terminal, an output terminal, an integration capacitor, and a reset switch;

a photo-detector connecting to said integrating input terminal of said integrating and summing amplifier;

a summing capacitor of which a first electrode is connected to output of prior TDI stage and a second electrode is connected to said summing input terminal of said integrating and summing amplifier;

a correlated double sample and hold (CDS) circuit comprising a plural of switches and a plural of storage circuits, having an input terminal connected to said output terminal of said integrating and summing amplifier, and an output terminal connected to summing capacitor of the following TDI stage; and

wherein said integrating and summing amplifier is first reset by closing said reset switch, and when said reset switch is subsequently open, the reset signal of said photo-detector and the reset signal stored in CDS circuit of said prior TDI stage are summed and immediately sampled and held by said CDS circuit;

thereafter said integrating and summing amplifier starts integrating photo-signal of said photo-detector and simultaneously sums integrated photo-signal of said photo-detector and the photo-signal stored in said CDS circuit of said prior TDI stage into a combined photo-signal which is sampled and held by said CDS circuit; and

consequently said combined photo-signal and said reset signal held in said CDS circuit are ready for transfer to said following TDI stage.

2. The CMOS TDI detector stage described in claim 1, wherein said integrating and summing amplifier comprises one or more stages.

3. The CMOS TDI detector stage described in claim 1, wherein said integrating input terminal and said summing input terminal are joined together into one input terminal, and further wherein said integration capacitor of said integrating and summing amplifier has its first electrode connected to said input terminal and its second electrode connected to said output terminal.

4. The CMOS TDI detector stage described in claim 3, wherein said integrating and summing amplifier is an analog amplifier, either with single or differential inputs.

5. The CMOS TDI detector stage described in claim 1, wherein said integrating and summing amplifier having a dual-stage amplifier with the first-stage amplifier performing the integration of said photo-signal and the second-stage performing the summing function, and furthermore the input of said first-stage amplifier becomes integrating input terminal of said integrating and summing amplifier, the input of said second-stage amplifier is connected to the output of said first-stage amplifier and becomes said summing input terminal of said integrating and summing amplifier, and output of said second-stage amplifier becomes said output terminal of said integrating and summing amplifier.

6. The CMOS TDI detector stage described in claim 5, wherein said first-stage amplifier is an analog amplifier with single or differential inputs, and furthermore said integration capacitor has its first electrode connected to said integrating input terminal and its second electrode connected to output of said first-stage amplifier.

7. The CMOS TDI detector stage described in claim 5, wherein said second-stage amplifier is an analog amplifier with single or differential inputs, and further having an additional capacitor of which its first electrode connected to said input of said second-stage amplifier and its second electrode connected to said output of said second-stage amplifier.

8. The CMOS TDI detector stage described in claim 1, wherein said photo-detector having a photo-sensitive diode capable of converting light into electrical current.

9. The CMOS TDI detector stage described in claim 1, wherein said storage circuit of said CDS circuit having a storage capacitor and a buffer amplifier.

10. The CMOS TDI detector stage described in claim 1, wherein said combined reset signal and said combined photo-signal are conveyed in parallel, independent storage circuits in said CDS circuit.

11. The CMOS TDI detector stage described in claim 1, wherein said combined reset signal and said combined photo-signal are both conveyed in a single chain of storage circuits;

furthermore said combined reset signal and said combined photo-signal are conveyed one-at-a-time through each storage circuit.

12. The CMOS TDI detector stage described in claim 1, wherein said photo-detector, said integrating and summing amplifier, and said CDS circuit are integrated on a single substrate, and further wherein a plurality of integrating and summing amplifiers and CDS circuits are physically isolated from a plurality of photo-detectors, so that the said plurality of integrating and summing amplifiers and CDS circuits may be shielded from harmful radiation while a plurality of photo-detectors is exposed to some harmful radiation in the process of receiving light.

13. A CMOS TDI detector stage comprising:

an integrating and summing amplifier having an integrating input terminal, a summing input terminal which may be joined to or may be separated from said integrating input terminal, an output terminal, an integration capacitor, and a reset switch;

a photo-detector connecting to said integrating input terminal of said integrating and summing amplifier;

a summing capacitor of which a first electrode is connected to output of prior TDI stage and a second electrode is connected to said summing input terminal of said integrating and summing amplifier;

a correlated double sample and hold (CDS) circuit comprising a plural of switches and a plural of storage circuits, having an input terminal connected to said output terminal of said integrating and summing amplifier, and an output terminal connected to summing capacitor of the following TDI stage; and

wherein said integrating and summing amplifier is first reset by closing said reset switch, and when said reset switch is subsequently open, the resulting reset signal is sampled and held by said CDS circuit;

thereafter said integrating and summing amplifier starts integrating photo-signal of said photo-detector and generates a cumulative signal that is the summation of integrated photo-signal of said photo-detector and the difference between the prior cumulative signal held in CDS circuit of said prior TDI stage and the reset signal held in said CDS circuit of said prior TDI stage;

furthermore said cumulative signal is sampled and held by said CDS circuit; and

consequently said cumulative signal and said reset signal held in said CDS circuit are ready for transfer to said following TDI stage.

14. The CMOS TDI detector stage described in claim 13, wherein said integrating and summing amplifier comprises one or more stages.

15. The CMOS TDI detector stage described in claim 13, wherein said integrating input terminal and said summing input terminal are joined together into one input terminal, and further wherein said integration capacitor of said integrating and summing amplifier has its first electrode connected to said input terminal and its second electrode connected to said output terminal.

16. The CMOS TDI detector stage described in claim 15, wherein said integrating and summing amplifier is an analog amplifier, either with single or differential inputs.

17. The CMOS TDI detector stage described in claim 13, wherein said integrating and summing amplifier having a dual-stage amplifier with the first-stage amplifier performing the integration of said photo-signal and the second-stage performing the summing function, and furthermore the input of said first-stage amplifier becomes integrating input terminal of said integrating and summing amplifier, the input of said second-stage amplifier is connected to the output of said first-stage amplifier and becomes said summing input terminal of said integrating and summing amplifier, and output of said second-stage amplifier becomes said output terminal of said integrating and summing amplifier.

18. The CMOS TDI detector stage described in claim 17, wherein said first-stage amplifier is an analog amplifier with single or differential inputs, and furthermore said integration capacitor has its first electrode connected to said integrating input terminal and its second electrode connected to output of said first-stage amplifier.

19. The CMOS TDI detector stage described in claim 17, wherein said second-stage amplifier is an analog amplifier with single or differential inputs, and further having an additional capacitor of which its first electrode connected to said input of said second-stage amplifier and its second electrode connected to said output of said second-stage amplifier.

20. The CMOS TDI detector stage described in claim 13, wherein said photo-detector having a photo-sensitive diode capable of converting light into electrical current.

21. The CMOS TDI detector stage described in claim 13, wherein said storage circuit of said CDS circuit having a storage capacitor and a buffer amplifier.

22. The CMOS TDI detector stage described in claim 13, wherein said reset signal and said cumulative signal are conveyed in parallel, independent storage circuits in said CDS circuit.

23. The CMOS TDI detector stage described in claim 13, wherein said reset signal and said cumulative signal are both conveyed in a single chain of storage circuits;

furthermore said reset signal and said cumulative signal are conveyed one-at-a-time through each storage circuit.

24. The CMOS TDI detector stage described in claim 13, wherein said photo-detector, said integrating and summing amplifier, and said CDS circuit are integrated on a single substrate, and further wherein a plurality of integrating and summing amplifiers and CDS circuits are physically isolated from a plurality of photo-detectors, so that said plurality of integrating and summing amplifiers and CDS circuits may be shielded from harmful radiation while a plurality of photo-detectors is exposed to some harmful radiation in the process of receiving light.