Semiconductor integrated circuit device

• US 8,040,187 B2
• Filed: 09/09/2009
• Issued: 10/18/2011
• Est. Priority Date: 03/31/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Deguchi, Jun, Kobayashi, Naoki
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): NGUYEN, KHIEM D
• Application Number:
  US12/556,115
• Publication Number:
  US 20100244964A1
• Time in Patent Office: 769 Days
• Field of Search: 330295-296, 330/253, 330/277
• US Class Current: 330/296
• CPC Class Codes: H03F 2200/453 Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
• CPC Class Codes: H03F 2203/45236 Two dif amps realised in MOS or JFET technology, one of them being of the p-channel type and the other one of the n-channel type, are coupled in parallel with their gates
• CPC Class Codes: H03F 2203/45244 the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
• CPC Class Codes: H03F 2203/45394 the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 2203/45528 the FBC comprising one or more passive resistors and being coupled between the LC and the IC
• CPC Class Codes: H03F 2203/45544 the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45696 the LC comprising more than two resistors
• CPC Class Codes: H03F 2203/45698 the LC comprising one or more resistors coupled to the LC by feedback (active or passive)
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/3028 with symmetrical driving of the end stage
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/505 with field-effect devices

Abstract

A semiconductor integrated circuit device constituting an inverting amplifier employs a cascode current source as a current source. In the semiconductor integrated circuit device, a high-potential-side transistor of the cascode current source and a low-potential-side transistor constituting an amplification portion are shared. The configuration can not only make an output impedance of the cascode current source high and improve current source characteristics but also make a minimum potential at a minimum potential point of the amplification portion low and ensure a sufficient power supply voltage margin.

Claims

1. A semiconductor integrated circuit device comprising:

an amplification portion including a first transistor configured to inversely amplify an input signal inputted to a gate and output the inversely amplified input signal from a drain;

a cascode current source including the first transistor, a second transistor having a drain connected to a source of the first transistor and a source connected to a reference potential point to supply a bias current to the first transistor, a third transistor having a gate to which only a DC component out of an AC component and the DC component included in a voltage applied to the gate of the first transistor is applied, a fourth transistor having a gate connected to a gate of the second transistor, and a current source, and configured to control the bias current based on a current flowing into the current source; and

a first element portion configured to block an AC signal and pass through a DC signal between the drain of the first transistor and the gates of the first and third transistors.

2. The semiconductor integrated circuit device according to claim 1, wherein

in the cascode current source,

the third transistor has a drain connected to the current source and the gate of the fourth transistor and a source connected to a drain of the fourth transistor,

a source of the fourth transistor is connected to a reference potential point, and

a mirror current flowing into the current source is applied to a drain-to-source path of the second transistor.

3. The semiconductor integrated circuit device according to claim 1, further comprising:

a load circuit connected between a power supply terminal and the drain of the first transistor.

4. The semiconductor integrated circuit device according to claim 1, further comprising:

a fifth transistor having a gate to which the input signal is inputted, a source connected to a power supply terminal, and a drain connected to the drain of the first transistor.

5. The semiconductor integrated circuit device according to claim 1, further comprising:

a sixth transistor having a source commonly connected to the source of the first transistor, the sixth transistor and the first transistor constituting a differential pair; and

a second element portion configured to block an AC signal and pass through a DC signal between a drain of the sixth transistor and gates of the sixth and third transistors.

6. The semiconductor integrated circuit device according to claim 5, further comprising:

a fifth transistor having a gate to which the input signal is inputted, a source connected to a power supply terminal, and a drain connected to the drain of the first transistor; and

a seventh transistor having a gate to which an inverted signal of the input signal is inputted, a source connected to a power supply terminal, and a drain connected to the drain of the sixth transistor.

7. The semiconductor integrated circuit device according to claim 1, wherein

the first element portion comprises

a first resistive element configured to block an AC signal and pass through a DC signal between the drain of the first transistor and the gate of the third transistor, and

a second resistive element configured to block an AC signal and pass through a DC signal between the drain and the gate of the first transistor.

8. The semiconductor integrated circuit device according to claim 5, wherein

the first element portion comprises

a first resistive element configured to block an AC signal and pass through a DC signal between the drain of the first transistor and the gate of the third transistor, and

a second resistive element configured to block an AC signal and pass through a DC signal between the drain and the gate of the first transistor, and

the second element portion comprises

a third resistive element configured to block an AC signal and pass through a DC signal between the drain of the sixth transistor and the gate of the third transistor, and

a fourth resistive element configured to block an AC signal and pass through a DC signal between the drain and the gate of the sixth transistor.

9. A semiconductor integrated circuit device comprising:

an amplification portion having a first transistor configured to inversely amplify an input signal inputted to a gate and output the inversely amplified input signal from a drain;

a second transistor having a drain connected to a source of the first transistor and a source connected to a reference potential point to supply a bias current to the first transistor;

a cascode current source composed of an eighth transistor and a ninth transistor which have same characteristics as the first and second transistors, respectively, a 10th transistor having a gate connected to a gate of the eighth transistor, an 11th transistor having a gate connected to a gate of the ninth transistor, and a current source, and configured to control the bias current based on a current flowing into the current source; and

a first element portion configured to block an AC signal and pass through a DC signal between the drain and the gate of the first transistor.

10. The semiconductor integrated circuit device according to claim 9, wherein

in the cascode current source,

the 10th transistor has a drain connected to the current source and the gate of the 11th transistor and a source is connected to a drain of the 11th transistor,

a source of the 11th transistor is connected to a reference potential point, and

a mirror current flowing into the current source is applied to a drain-to-source path of the second transistor.

11. The semiconductor integrated circuit device according to claim 9, further comprising:

a load circuit connected between a power supply terminal and the drain of the first transistor.

12. The semiconductor integrated circuit device according to claim 9, further comprising:

a fifth transistor having a gate to which the input signal is inputted, a source connected to a power supply terminal, and a drain connected to the drain of the first transistor.

13. The semiconductor integrated circuit device according to claim 9, further comprising:

a sixth transistor having a source commonly connected to the source of the first transistor, the sixth transistor and the first transistor constituting a differential pair; and

a second element portion configured to block an AC signal and pass through a DC signal between a drain and a gate of the sixth transistor.

14. The semiconductor integrated circuit device according to claim 13, further comprising:

a fifth transistor having a gate to which the input signal is inputted, a source connected to a power supply terminal, and a drain connected to the drain of the first transistor; and

a seventh transistor having a gate to which an inverted signal of the input signal is inputted, a source connected to a power supply terminal, and a drain connected to the drain of the sixth transistor.

15. The semiconductor integrated circuit device according to claim 9, wherein

the first element portion is composed of a resistive element.

16. The semiconductor integrated circuit device according to claim 13, wherein

the first and second element portions are each composed of a resistive element.