Programmable sigma-delta analog-to-digital converter

• US 8,040,266 B2
• Filed: 03/31/2008
• Issued: 10/18/2011
• Est. Priority Date: 04/17/2007
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Thiagarajan, Eashwar, Sivadasan, Mohandas Palatholmana, Rohilla, Gajender, Kutz, Harold, Mar, Monte
• Primary Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US12/060,128
• Publication Number:
  US 20080297388A1
• Time in Patent Office: 1,296 Days
• Field of Search: 341/143, 341/155, 341/141, 341/166
• US Class Current: 341/143
• CPC Class Codes: H03M 3/394 among different orders of the loop filter
• CPC Class Codes: H03M 3/438 the modulator having a higher order loop filter in the feedforward path

Abstract

A system includes an analog-to-digital modulator to convert at least one analog input signal into at least one digital output signal. The system also includes a processing device to set an operational order and a quantization level of the analog-to-digital modulator. The analog-to-digital modulator converts the analog input signal into the digital output signal according to the operational order and the quantization level.

Claims

1. A system comprising:

an analog-to-digital modulator to convert at least one analog input signal into at least one digital output signal, where the analog-to-digital modulator includes a variable stage integration circuit to perform integration operations on the analog input signal according to an operational order; and

a processing device to set the operational order and a quantization level of the analog-to-digital modulator, the analog-to-digital modulator to convert the analog input signal into the digital output signal according to the operational order and the quantization level wherein the processing device determines a feedback reference voltage to optimize performance trade-offs in the system.

2. The system of claim 1, where the variable stage integration circuit includes multiple integrators to perform integration operations on the analog input signal, the processing device to set the operational order of the analog-to-digital modulator by dynamically selecting one or more of the integrators to perform integration operations on the analog input signal.

3. The system of claim 1, where the analog-to-digital modulator includes a quantization circuit to generate the digital output signal from the integrated analog input signal according to the quantization level set by the processing device.

4. The system of claim 3, where the quantization circuit includes multiple comparators, when dynamically selected by the processing device, to compare the integrated analog input signal from the variable stage integration circuit with one or more programmable reference thresholds, the processing device to control voltage levels associated with the programmable reference thresholds.

5. The system of claim 1, where the analog-to-digital modulator includes a feedback circuit to generate a digital feedback signal based, at least in part, on the digital output signal, the processing device to control an introduction of the feedback reference voltage to the variable stage integration circuit responsive to the digital feedback signal.

6. The system of claim 5, where the analog-to-digital modulator includes a reconfigurable reference capacitance circuit having a plurality of capacitors capable of supplying corresponding capacitance voltages to the variable stage integration circuit as the feedback reference voltage, the processing device to select one or more of the capacitors to supply the associated capacitance voltages to the variable stage integration circuit.

7. A method comprising:

setting both an operational order of an integration circuit and a quantization level of a quantization circuit, where the operational order of the integration circuit and the quantization level of the quantization circuit are reconfigurable, and where the operational order of the integration circuit indicates a number of analog integrators utilized by the integration circuit to integrate the analog input signal;

integrating an analog input signal according to the operational order of the integration circuit; and

generating a digital output signal from the integrated analog input signal according to the quantization level of the quantization circuit wherein a processing device determines a feedback reference voltage to optimize performance trade-offs in the system.

8. The method of claim 7 where the quantization level of the quantization circuit indicates a number of comparators utilized by the quantization circuit to generate the digital output signal.

9. The method of claim 8, where the comparators, when selected according to the quantization level, each generate one bit of the digital output signal from the integrated analog signal per audio sample.

10. The method of claim 8, includes providing programmable voltage thresholds to the comparators, where the comparators are configured to compare the integrated analog signal to the corresponding programmable voltage thresholds when generating the digital output signal from the integrated analog signal.

11. The method of claim 7, includes

generating the digital feedback signal from the digital output signal;

and

supplying a feedback reference voltage to integration circuit according to the digital feedback signal.

12. The method of claim 11, includes selecting one or more capacitors to supply the feedback reference voltage to the integration circuit according to the digital feedback signal.

13. A device comprising:

an integration circuit to perform integration operations on at least one analog input signal according to a reconfigurable operational order of the integration circuit, where the integration circuit includes multiple analog integrators to integrate the analog input signal, the reconfigurable operational order to indicate a number of the analog integrators the integration circuit utilizes to perform integration operations on the analog input signal; and

a quantization circuit to generate at least one digital output signal from the integrated analog input signal according to a reconfigurable quantization level of the quantization circuit wherein a processing device determines a feedback reference voltage to optimize performance trade-offs in the system.

14. The device of claim 13, where the quantization circuit includes multiple comparators to compare the integrated analog input signal from the integration circuit with one or more programmable reference thresholds.

15. The device of claim 13, where the reconfigurable quantization level to indicate a number of the comparators the quantization circuit utilizes generate at least one digital output signal from the integrated analog input signal.

16. The device of claim 15, where the reconfigurable quantization level indicates a number of bits representing the digital output signal per audio sample.

17. The device of claim 13, including

a feedback circuit to generate a digital feedback signal based, at least in part, on the digital output signal;

and

a reference capacitance circuit having a plurality of selectable capacitors, each capable of providing an input reference voltage to the integration circuit according to the digital feedback signal.