Power converter disable verification system and method

• US 8,046,179 B2
• Filed: 10/06/2008
• Issued: 10/25/2011
• Est. Priority Date: 10/06/2008
• Status: Active Grant

• Current Assignee: Rockwell Automation Technologies Incorporated (Allen-Bradley Co., Inc.)
• Original Assignee: Rockwell Automation Technologies Incorporated (Allen-Bradley Co., Inc.)
• Inventors: Seidlitz, Steven Terry, Campbell, Alan J, Tallam, Rangarajan M, Yegorov, Alex
• Primary Examiner(s): Bui; Bryan
• Application Number:
  US12/245,992
• Publication Number:
  US 20100088047A1
• Time in Patent Office: 1,114 Days
• Field of Search: 702/58, 318/491, 327/108, 323/282, 361/103
• US Class Current: 702/58
• CPC Class Codes: H02P 29/02 Providing protection against overload without automatic interruption of supply protection against faults of stepper motors H02P8/36

Abstract

A power electronics device with an improved IGBT protection mechanism is provided. More specifically, systems and methods are provided for shortening the duration of a shutdown test pulse, such that the power output to the load is substantially unaffected.

Claims

1. A motor control system, comprising:

an inverter module comprising a solid state switch configured to generate an output power waveform for powering the motor;

driver circuitry communicatively coupled to the inverter module and configured to activate and deactivate the solid state switch for generating the output power waveform;

shutdown circuitry coupled to the driver circuitry and configured to disable the driver circuitry; and

control circuitry coupled to the driver circuitry and the shutdown circuitry and configured to communicate with the driver circuitry and the shutdown circuitry;

wherein the shutdown circuitry is configured to perform a shutdown diagnostic test that verifies the ability of the shutdown circuitry to disable the driver circuitry by disabling the driver circuitry for a time period that is short enough to prevent the solid state switch from changing state.

2. The motor control system of claim 1, comprising an input device electrically coupled to a gate of the solid state switch and configured to receive an input pulse from the driver circuitry and send a corresponding output pulse to the solid state switch to turn on the solid state switch, wherein the input device imparts a time delay between a termination of the input pulse and a termination of the output pulse, and wherein the shutdown circuitry is configured to generate a test pulse that disables the driver circuitry for a time period that is shorter than the time delay.

3. The motor control system of claim 2, wherein the input device comprises an opto-coupler.

4. The motor control system of claim 1, wherein the shutdown circuitry comprises a shutdown processor configured to conduct the shutdown diagnostic test, disable circuitry configured to receive a shutdown command from the shutdown circuitry and send a corresponding test pulse to the driver circuitry, and result circuitry configured to receive a status signal from the driver circuitry indicating whether the driver circuitry is enabled or disabled.

5. The motor control system of claim 4, wherein the result circuitry includes a first latch and wherein an output of the first latch is coupled to the disable circuitry and configured to re-enable the driver circuitry upon receiving the status signal from the driver circuitry.

6. The motor control system of claim 4, wherein the result circuitry stores the status signal from the driver circuitry until the shutdown processor has processed the results of the shutdown diagnostic test.

7. The motor control system of claim 4, wherein the result circuitry includes pulse conditioning circuitry configured to increase a duration of the test pulse.

8. The motor control system of claim 4, wherein the disable circuitry includes a second latch, wherein the output of the second latch is configured to initiate the test pulse, and wherein the output of the first latch is configured to terminate the test pulse.

9. The motor control system of claim 4, wherein the disable circuitry includes a full shutdown circuitry configured to disable the driver circuitry in response to a shutdown command that persists for a specified duration.

10. The motor control system of claim 4, wherein the disable circuitry comprises an AND-gate with a first input coupled to a shutdown-command output of the shutdown processor and a second input coupled to an output of the first latch.

11. The motor control system of claim 10, wherein the shutdown processor includes a pulse-test-enable output coupled to the reset input of the first latch, wherein the pulse-test-enable output is configured to determine whether a full shutdown or a shutdown diagnostic test is performed and whether the shutdown circuitry is functioning properly.

12. The motor control system of claim 10, wherein the pulse-test-enable output is configured to cause a full shutdown by holding the first latch in a reset mode while sending the shutdown command to the driver circuitry.

13. A method of operating a motor drive, comprising:

sending signals from a control circuitry to a driver circuitry;

sending drive pulses from the driver circuitry to an inverter input device;

sending output pulses corresponding to the drive pulses from the inverter input device to a solid state switch to generate an output power waveform; and

performing a test configured to temporarily disable the driver circuitry;

wherein the inverter input device causes a time delay between a termination of the drive pulses input and a termination of the output pulses, and wherein duration of the test is shorter than the time delay.

14. The method of claim 13, wherein the inverter input device includes an opto-coupler.

15. The method of claim 13, wherein performing the test comprises:

sending a shutdown command from a shutdown processor to a disable circuitry;

sending a disable command corresponding to the shutdown command from the disable circuitry to the driver circuitry;

sending a status signal from the driver circuitry to a result circuitry;

sending a power-up command from the result circuitry to the disable circuitry;

sending a re-enable command from the disable circuitry to the drive circuitry.

16. The method of claim 13, wherein the test is approximately fifty to one hundred fifty nano-seconds in duration.

17. The method of claim 13, comprising receiving a status signal from the driver circuitry in response to the test, storing the status signal in a result circuitry, and sending the status signal from the result circuitry to the shutdown processor.

18. A method of performing a shutdown diagnostic test in a motor drive, comprising:

receiving a full shutdown command from a motor control circuitry;

sending a pulse-test-enable command from a processor to a reset input of a latch, the pulse-test-enable signal enabling the latch to change state in response to a clock input of the latch;

sending a shutdown command from the processor to a disable circuitry;

sending a disable command from the disable circuitry to a driver circuitry in response to the shutdown command;

sending a status indicator from the driver circuitry to the clock input of the latch in response to the disable command, the status indicator causing the latch to change state; and

sending a power-up command from the latch to the disable circuitry, the power-up command over-riding the shutdown command from the processor.

19. The method of claim 18, comprising sending a test-result indicator corresponding to the status indicator from the latch to the processor.

20. The method of claim 19, comprising sending a fault indicator from the processor to the motor control circuitry if the test-result indicator indicates a failure to disable the driver circuitry.

21. The method of claim 18, comprising:

terminating the pulse-test-enable command from the processor, thereby causing the latch to reset;

terminating the shutdown command from the processor, thereby causing the driver to be re-enabled;

sending a test-result indicator from an output of a NAND-gate to the processor, wherein a first input of the NAND-gate receives the status indictor and a second input of the NAND-gate receives an output of the latch.

22. A method of performing a diagnostic test in a motor drive, comprising:

sending a disable signal from a control circuitry to a driver circuitry, the disable signal causing the driver circuitry to stop sending drive signals to an inverter module;

receiving a status signal from the driver circuitry, the status signal indicating that the driver circuitry has been disabled; and

sending a re-enable signal to the driver circuitry that causes the driver circuitry to resume sending drive signals to the inverter module;

wherein the re-enable signal is sent to the driver circuitry before the inverter module disrupts the sending of power to the motor in response to the disable signal.