Integrated circuit, semiconductor device comprising the same, electronic device having the same, and driving method of the same

• US 8,049,219 B2
• Filed: 12/23/2010
• Issued: 11/01/2011
• Est. Priority Date: 03/11/2003
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): Auduong; Gene N.
• Application Number:
  US12/977,143
• Publication Number:
  US 20110089426A1
• Time in Patent Office: 313 Days
• Field of Search: 365/149, 365108-109, 365/184, 365/189.01, 257/66, 257 71- 72, 257365-366, 257/E27.084, 257/E29.273, 257/E33.053, 438/157, 438/176
• US Class Current: 257/66
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

An integrated circuit mounting a DRAM which can realize high integration without complicated manufacturing steps. The integrated circuit according to the invention comprises a DRAM in which a plurality of memory cells each having a thin film transistor are disposed. The thin film transistor comprises an active layer including a channel forming region, and first and second electrodes overlapping with each other with the channel forming region interposed therebetween. By controlling a drain voltage of the thin film transistor according to data, it is determined whether to accumulate holes in the channel forming region or not, and data is read out by confirming whether or not holes are accumulated.

Claims

1. A semiconductor device comprising:

a DRAM over a substrate, the DRAM including;

a transistor comprising;

a first gate electrode over the substrate;

a semiconductor film over the first gate electrode wherein the first gate electrode and the semiconductor film overlap each other with a first insulating layer interposed therebetween; and

a second gate electrode over the semiconductor film wherein the semiconductor film and the second gate electrode overlap each other with a second insulating layer interposed therebetween;

a first line electrically connected to the semiconductor film; and

a second line electrically connected to the semiconductor film,

wherein the semiconductor film comprises a channel forming region,

wherein data is represented by an amount of holes which are accumulated in the channel forming region, and

wherein holes are accumulated in the channel forming region by impact ionization.

2. The semiconductor device according to the claim 1, wherein an amount of holes accumulated in the channel forming region is adjusted by controlling a voltage applied to the first gate electrode.

3. The semiconductor device according to the claim 1, wherein data stored in the transistor is read out by using a drain current or a threshold voltage of the transistor.

4. The semiconductor device according to claim 1, wherein the semiconductor film comprises silicon.

5. The semiconductor device according to claim 1, wherein the first gate electrode is connected to a first word line and the second gate electrode is connected to a second word line.

6. A semiconductor device comprising:

a first portion over a substrate, the first portion including;

a first transistor comprising;

a first gate electrode over the substrate;

a first semiconductor film over the first gate electrode wherein the first gate electrode and the first semiconductor film overlap each other with a first insulating layer interposed therebetween; and

a second gate electrode over the first semiconductor film wherein the first semiconductor film and the second gate electrode overlap each other with a second insulating layer interposed therebetween;

a first line electrically connected to the first semiconductor film; and

a second line electrically connected to the first semiconductor film; and

a second portion over the substrate, the second portion including;

a second transistor comprising;

a second semiconductor film over the substrate; and

a third gate electrode over the second semiconductor film wherein the second semiconductor film and the third gate electrode overlap each other with the second insulating layer;

a wiring electrically connected to the second semiconductor film;

a first electrode electrically connected to the wiring;

a light emitting layer over the first electrode; and

a second electrode over the light emitting layer,

wherein the first semiconductor film comprises a channel forming region.

7. The semiconductor device according to the claim 6,

wherein data is represented by an amount of holes which are accumulated in the channel forming region, and

wherein holes are accumulated in the channel forming region by impact ionization.

8. The semiconductor device according to the claim 6, wherein an amount of holes accumulated in the channel forming region is adjusted by controlling a voltage applied to the first gate electrode.

9. The semiconductor device according to the claim 6, wherein data stored in the first transistor is read out by using a drain current or a threshold voltage of the first transistor.

10. The semiconductor device according to claim 6, wherein the second transistor is a transistor for controlling a current supply.

11. The semiconductor device according to claim 6, wherein the first semiconductor film is an n-channel transistor and the second semiconductor film is a p-channel transistor.

12. The semiconductor device according to claim 6, wherein the first gate electrode is connected to a first word line and the second gate electrode is connected to a second word line.

13. A semiconductor device comprising:

a first portion over a substrate, the first portion including;

a first transistor comprising;

a first gate electrode over the substrate;

a first semiconductor film over the first gate electrode wherein the first gate electrode and the first semiconductor film overlap each other with a first insulating layer interposed therebetween; and

a second gate electrode over the first semiconductor film

wherein the first semiconductor film and the second gate electrode overlap each other with a second insulating layer interposed therebetween; and

a source line electrically connected to the first semiconductor film; and

a second portion over the substrate, the second portion including;

a second transistor comprising;

a second semiconductor film over the substrate; and

a third gate electrode over the second semiconductor film

wherein the second semiconductor film and the third gate electrode overlap each other with the second insulating layer; and

a bit line electrically connected to one of a source and a drain of the second transistor;

wherein the first semiconductor film comprises a channel forming region, and

wherein one of a source and a drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor.

14. The semiconductor device according to the claim 13,

wherein data is represented by an amount of holes which are accumulated in the channel forming region, and

wherein holes are accumulated in the channel forming region by impact ionization.

15. The semiconductor device according to the claim 13, wherein an amount of holes accumulated in the channel forming region is adjusted by controlling a voltage applied to the first gate electrode.

16. The semiconductor device according to the claim 13, wherein data stored in the first transistor is read out by using a drain current or a threshold voltage of the first transistor.

17. The semiconductor device according to claim 13, wherein the second transistor is a transistor for controlling a current supply.

18. The semiconductor device according to claim 13, wherein the first semiconductor film is an n-channel transistor and the second semiconductor film is a p-channel transistor.

19. The semiconductor device according to claim 13, wherein the first gate electrode is connected to a first word line and the second gate electrode is connected to a second word line.