Distortion estimation and cancellation in memory devices

• US 8,050,086 B2
• Filed: 05/10/2007
• Issued: 11/01/2011
• Est. Priority Date: 05/12/2006
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Gurgi, Eyal, Shalvi, Ofir, Sommer, Naftali, Maislos, Ariel
• Primary Examiner(s): Hur; J. H.
• Application Number:
  US11/995,801
• Publication Number:
  US 20080198650A1
• Time in Patent Office: 1,636 Days
• Field of Search: 365/185.02, 365/185.03, 365/185.09, 711/103, 714/721
• US Class Current: 365/185.02
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.

Claims

1. A method for operating a memory, comprising:

storing data in a group of analog memory cells of the memory as respective first voltage levels, selected from a set of possible values corresponding to respective possible combinations of data bits to be stored in the analog memory cells;

after storing the data, reading from the analog memory cells respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels;

processing the second voltage levels to derive respective hard decisions, each hard decision specifying a respective combination of the data bits selected from among the possible combinations of the data bits;

calculating respective differences between the second voltage levels that were read from the analog memory cells and the respective first voltage levels corresponding to the hard decisions;

estimating cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, based on the differences; and

reconstructing the data stored in the group of analog memory cells from the read second voltage levels using the estimated cross-coupling coefficients.

2. The method according to claim 1, wherein estimating the cross-coupling coefficients comprises processing the second voltage levels and the respective hard decisions using a block estimation process.

3. The method according to claim 1, wherein estimating the cross-coupling coefficients comprises sequentially scanning the second voltage levels and the respective hard decisions using a sequential estimation process that converges to the cross-coupling coefficients.

4. The method according to claim 1, wherein estimating the cross-coupling coefficients comprises applying an estimation process that reduces a distance metric between the read second voltage levels and the respective hard decisions.

5. The method according to claim 1, and comprising evaluating the cross-coupling interference caused by a first analog memory cell to a second analog memory cell in the memory based on both the second voltage level read from the first analog memory cell and on the second voltage level read from the second analog memory cell.

6. The method according to claim 1, wherein reconstructing the data comprises removing the cross-coupling interference from the second voltage levels using one of a linear equalization process, a Decision-Feedback Equalization (DFE) process, a Maximum a Posteriori (MAP) estimation process and a Maximum-Likelihood Sequence Estimation (MLSE) process.

7. The method according to claim 1, wherein estimating the cross-coupling coefficients and reconstructing the data comprise estimating the cross-coupling coefficients in a first processing stage, and canceling the estimated cross-coupling interference in a second processing stage subsequent to the first processing stage.

8. The method according to claim 7, wherein estimating the cross-coupling coefficients and reconstructing the data comprise using the estimated cross-coupling coefficients for subsequent instances of the second processing stage.

9. The method according to claim 8, and comprising repeating the first processing stage only upon failure to reconstruct the data.

10. The method according to claim 1, wherein storing the data comprises encoding the data using an Error Correcting Code (ECC), wherein reconstructing the data comprises computing error correction metrics based on the estimated cross-coupling coefficients and decoding the ECC using the error correction metrics.

11. A method for operating a memory, comprising:

storing data in a group of analog memory cells of the memory as respective first voltage levels;

after storing the data, reading from the analog memory cells respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels;

estimating cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells by processing the second voltage levels; and

reconstructing the data stored in the group of analog memory cells from the read second voltage levels using the estimated cross-coupling coefficients.

12. The method according to claim 11, and comprising evaluating the cross-coupling interference caused by a first analog memory cell to a second analog memory cell in the memory based on both the second voltage level read from the first analog memory cell and on the second voltage level read from the second analog memory cell.

13. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to store data in a group of the analog memory cells as respective first voltage levels selected from a set of possible values corresponding to respective possible combinations of data bits to be stored in the analog memory cells, to read from the analog memory cells, after storing the data, respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels, to process the second voltage levels to derive respective hard decisions, each hard decision specifying a respective combination of the data bits selected from among the possible combinations of the data bits, to calculate respective differences between the second voltage levels that were read from the analog memory cells and the respective first voltage levels corresponding to the hard decisions, to estimate cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, based on the differences, and to reconstruct the data stored in the group of analog memory cells from the second voltage levels using the estimated cross-coupling coefficients.

14. The apparatus according to claim 13, wherein the MSP is arranged to estimate the cross-coupling coefficients by processing the second voltage levels and the respective hard decisions using a block estimation process.

15. The apparatus according to claim 13, wherein the MSP is arranged to estimate the cross-coupling coefficients by sequentially scanning the second voltage levels and the respective hard decisions using a sequential estimation process that converges to the cross-coupling coefficients.

16. The apparatus according to claim 13, wherein the MSP is arranged to apply an estimation process that reduces a distance metric between the read second voltage levels and the respective hard decisions.

17. The apparatus according to claim 13, wherein the MSP is arranged to evaluate the cross-coupling interference caused by a first analog memory cell to a second analog memory cell in the memory based on both the second voltage level read from the first analog memory cell and on the second voltage level read from the second analog memory cell.

18. The apparatus according to claim 13, wherein the MSP is arranged to remove the cross-coupling interference from the second voltage levels using one of a linear equalization process, a Decision-Feedback Equalization (DFE) process, a Maximum a Posteriori (MAP) estimation process and a Maximum-Likelihood Sequence Estimation (MLSE) process.

19. The apparatus according to claim 13, wherein the MSP is arranged to estimate the cross-coupling coefficients in a first processing stage, and to cancel the estimated cross-coupling interference in a second processing stage subsequent to the first processing stage.

20. The apparatus according to claim 19, wherein the MSP is arranged to use the estimated cross-coupling coefficients for subsequent instances of the second processing stage.

21. The apparatus according to claim 20, wherein the MSP is arranged to repeat the first processing stage only upon failure to reconstruct the data.

22. The apparatus according to claim 13, wherein the MSP is arranged to encode the data using an Error Correcting Code (ECC) before storing the data, to compute error correction metrics based on the estimated cross-coupling coefficients and to reconstruct the data by decoding the ECC using the error correction metrics.

23. A data storage apparatus, comprising:

an interface, which is operative to communicate with a memory that includes a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the interface and is arranged to store data in a group of the analog memory cells of the memory as respective first voltage levels, to read from the analog memory cells, after storing the data, respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels, to estimate cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells by processing the second voltage levels, and to reconstruct the data stored in the group of analog memory cells from the read second voltage levels using the estimated cross-coupling coefficients.

24. The apparatus according to claim 23, wherein the MSP is arranged to evaluate the cross-coupling interference caused by a first analog memory cell to a second analog memory cell in the memory based on both the second voltage level read from the first analog memory cell and on the second voltage level read from the second analog memory cell.

25. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to store data in a group of the analog memory cells as respective first voltage levels selected from a set of possible values corresponding to respective possible combinations of data bits to be stored in the analog memory cells, to read from the analog memory cells, after storing the data, respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels, to process the second voltage levels to derive respective hard decisions, each hard decision specifying a respective combination of the data bits selected from among the possible combinations of the data bits, to calculate respective differences between the second voltage levels that were read from the analog memory cells and the respective first voltage levels corresponding to the hard decisions, to estimate cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, based on the differences, and to reconstruct the data stored in the group of analog memory cells from the second voltage levels using the cross-coupling coefficients.

26. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

a memory signal processor (MSP), which is coupled to the memory and is arranged to store data in a group of the analog memory cells of the memory as respective first voltage levels, to read from the analog memory cells, after storing the data, respective second voltage levels, which are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels, to estimate cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells by processing the second voltage levels, and to reconstruct the data stored in the group of analog memory cells from the read second voltage levels using the estimated cross-coupling coefficients.