Flash memory with coding and signal processing

• US 8,055,979 B2
• Filed: 11/08/2006
• Issued: 11/08/2011
• Est. Priority Date: 01/20/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Pantas, Wu, Zining
• Primary Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US11/598,178
• Publication Number:
  US 20070171714A1
• Time in Patent Office: 1,826 Days
• Field of Search: 714/773, 714/755
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be a flash EEPROM array. The memory unit optionally includes a modulator and a demodulator. The data modulated by the modulator is stored in the memory array. The demodulator demodulates the modulated data retrieved from the memory array.

Claims

1. A solid state non-volatile memory unit comprising:

a first encoder configured to generate first encoded data;

a second encoder in communication with the first encoder, the second encoder configured to generate second encoded data based on the first encoded data;

a multi-level solid state non-volatile memory array configured to store the second encoded data encoded by the second encoder, the multi-level solid state non-volatile memory array utilizing a predetermined number of digital levels to store the second encoded data;

a demodulator configured to generate a signal based on the second encoded data, the signal being characterized by a number of possible values that is greater than the predetermined number of digital levels used to store the second encoded data;

a first decoder configured to decode the second encoded data retrieved from the multi-level solid state non-volatile memory array; and

a second decoder in communication with the first decoder, the second decoder configured to decode an output of the first decoder,

wherein at least the first decoder processes the signal generated by the demodulator.

2. The solid state non-volatile memory unit of claim 1 wherein the multi-level solid state non-volatile memory array is a flash EEPROM array.

3. The solid state non-volatile memory unit of claim 1 wherein the first encoder is configured to execute a first ECC technique different from a second ECC technique executed by the second encoder.

4. The solid state non-volatile memory unit of claim 1 wherein the first encoder comprises a Reed-Solomon encoder.

5. The solid state non-volatile memory unit of claim 1 further comprising:

a modulator configured to modulate the second encoded data to generate modulated data,

wherein the demodulator is further configured to demodulate the modulated data retrieved from the multi-level solid state non-volatile memory array.

6. The solid state non-volatile memory unit of claim 1 wherein the second encoder is a binary encoder.

7. The solid state non-volatile memory unit of claim 6 wherein the binary encoder encodes in accordance with a binary code selected from a group consisting of Hamming code, BCH code, Reed-Muller code and Array Code.

8. The solid state non-volatile memory unit of claim 1 wherein the second encoder is selected from a group consisting of non-binary encoder and convolutional encoder.

9. The solid state non-volatile memory unit of claim 1 wherein the second encoder is disposed in a trellis-coded modulator.

10. The solid state non-volatile memory unit of claim 1 wherein the second encoder is an iterative encoder.

11. The solid state non-volatile memory unit of claim 10 wherein the iterative encoder encodes in accordance with a code selected from a group consisting of low-density parity check code and Turbo code.

12. The solid state non-volatile memory unit of claim 10 wherein the iterative encoder is a symbol-based iterative encoder.

13. The solid state non-volatile memory unit of claim 1 wherein the solid state non-volatile memory unit is disposed in an integrated circuit.

14. A method of operating a solid state non-volatile memory unit, the method comprising:

encoding a first data to generate first encoded data;

encoding the first encoded data to generate second encoded data;

storing the second encoded data in a multi-level solid state non-volatile memory array, the multi-level solid state non-volatile memory array utilizing a predetermined number of digital levels to store the second encoded data;

retrieving the second encoded data from the multi-level solid state non-volatile memory array;

generating a signal based on the second encoded data, the signal being characterized by a number of possible values that is greater than the predetermined number of digital levels used to store the second encoded data;

decoding the second encoded data retrieved from the multi-level solid state non-volatile memory array to generate decoded data; and

decoding the decoded data.

15. The method of claim 14 wherein the multi-level solid state non-volatile memory array is a flash EEPROM array.

16. The method of claim 14 wherein the encoding of the first data is performed in accordance with a first ECC technique different from a second ECC technique in accordance with which the first encoded data is encoded.

17. The method of claim 16 wherein the first ECC technique is a Reed-Solomon code.

18. The method of claim 14 further comprising:

modulating the second encoded data to generated modulated data;

storing the modulated data in the multi-level solid state non-volatile memory array;

retrieving the modulated data from the multi-level solid state non-volatile memory array; and

demodulating the modulated data retrieved from the multi-level solid state non-volatile memory array.

19. The method of claim 14 further comprising:

encoding the first encoded data in accordance with a binary code.

20. The method of claim 19 wherein the binary code is selected from a group consisting of Hamming code, BCH code, Reed-Muller code and Array Code.

21. The method of claim 14 further comprising:

encoding the first encoded data in accordance with one of non-binary code and convolutional code.

22. The method of claim 18 wherein the encoding of the first encoded data comprises trellis-coded modulation.

23. The method of claim 14 wherein the encoding of the first encoded data is an iterative encoding.

24. The method of claim 23 wherein the iterative encoding is performed in accordance with a code selected from a group consisting of low-density parity check code and Turbo code.

25. The method of claim 23 wherein the iterative encoding is a symbol-based iterative encoding.

26. A solid state non-volatile memory unit comprising:

means for encoding a first data to generate first encoded data;

means for encoding the first encoded data to generate second encoded data;

means for storing the second encoded data in a multi-level solid state non-volatile memory array, the multi-level solid state non-volatile memory array utilizing a predetermined number of digital levels to store the second encoded data;

means for retrieving the second encoded data from the multi-level solid state non-volatile memory array;

means for generating a signal based on the second encoded data, the signal being characterized by a number of possible values that is greater than the predetermined number of digital levels used to store the second encoded data;

means for decoding the second encoded data retrieved from the multi-level solid state non-volatile memory array; and

means for decoding an output of the means for decoding the second encoded data.

27. The solid state non-volatile memory unit of claim 26 wherein the multi-level solid state non-volatile memory array is a flash EEPROM array.

28. The solid state non-volatile memory unit of claim 26 wherein the means for encoding the first data is configured to execute a first ECC technique different from a second ECC technique executed by the means for encoding the means for encoding the first encoded data.

29. The solid state non-volatile memory unit of claim 28 wherein the first ECC technique is a Reed-Solomon code.

30. The solid state non-volatile memory unit of claim 26 further comprising:

means for modulating the second encoded data to generate modulated data;

means for storing the modulated data in the multi-level solid state non-volatile memory array;

means for retrieving the modulated data from the multi-level solid state non-volatile memory array; and

means for demodulating the modulated data retrieved from the multi-level solid state non-volatile memory array.

31. The solid state non-volatile memory unit of claim 26 wherein the means for encoding the first encoded data encodes in accordance with a binary code.

32. The solid state non-volatile memory unit of claim 28 wherein the means for encoding the first encoded data encodes in accordance with a binary code selected from a group consisting of Hamming code, BCH code, Reed-Muller code and Array Code.

33. The solid state non-volatile memory unit of claim 26 wherein the means for encoding the first encoded data is selected from a group consisting of non-binary encoder and convolutional encoder.

34. The solid state non-volatile memory unit of claim 30 wherein the means for encoding the first encoded data is disposed in a trellis-coded modulator.

35. The solid state non-volatile memory unit of claim 26 wherein the means for encoding the first encoded data is an iterative encoder.

36. The solid state non-volatile memory unit of claim 35 wherein the iterative encoder encodes in accordance with a code selected from a group consisting of low-density parity check code and Turbo code.

37. The solid state non-volatile memory unit of claim 35 wherein the iterative encoder is a symbol-based iterative encoder.