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Method of making a semiconductor chip assembly with a post/base heat spreader and horizontal signal routing

  • US 8,062,912 B2
  • Filed: 09/13/2009
  • Issued: 11/22/2011
  • Est. Priority Date: 03/25/2008
  • Status: Expired due to Fees
First Claim
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1. A method of making a semiconductor chip assembly, comprising:

  • providing a post, a base, an adhesive and a substrate, whereinthe substrate includes a first conductive layer, a second conductive layer and a dielectric layer therebetween,the post is adjacent to the base, extends above the base in an upward direction, extends through an opening in the adhesive and extends into an aperture in the substrate,the base extends below the post in a downward direction opposite the upward direction and extends laterally from the post in lateral directions orthogonal to the upward and downward directions,the adhesive is mounted on and extends above the base, is sandwiched between the base and the substrate and is non-solidified,the substrate is mounted on and extends above the adhesive, the first conductive layer extends above the dielectric layer, the dielectric layer extends above the second conductive layer, anda gap is located in the aperture between the post and the substrate;

    thenflowing the adhesive into and upward in the gap;

    solidifying the adhesive;

    thenproviding a pad and a terminal, including;

    grinding the post, the adhesive and the first conductive layer such that the post, the adhesive and the first conductive layer are laterally aligned with one another at a top lateral surface that faces in the upward direction; and

    thenremoving selected portions of the first conductive layer;

    thenmounting a semiconductor device on a heat spreader that includes the post and the base, wherein the semiconductor device overlaps the post, the substrate includes the pad, the terminal, a routing line and first and second vias, the pad and the terminal include selected portions of the first conductive layer, the routing line includes a selected portion of the second conductive layer and the vias each extend through the dielectric layer;

    electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal, wherein an electrically conductive path between the pad and the terminal includes the first via, the routing line and the second via; and

    thermally connecting the semiconductor device to the post, thereby thermally connecting the semiconductor device to the base.

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