Providing hardware independence to automate code generation of processing device firmware

• US 8,069,436 B2
• Filed: 08/10/2005
• Issued: 11/29/2011
• Est. Priority Date: 08/13/2004
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren, Maheshwari, Dinesh, Ogami, Kenneth, Hastings, Mark
• Primary Examiner(s): Zhen, Wei
• Assistant Examiner(s): Nahar, Qamrun
• Application Number:
  US11/200,619
• Publication Number:
  US 20060037007A1
• Time in Patent Office: 2,302 Days
• Field of Search: 717/106, 717/107, 717/108, 717/109, 717/140
• US Class Current: 717/106
• CPC Class Codes: G06F 8/30 Creation or generation of source code
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57

Abstract

A user application is generated in response to user input, wherein the user application is described in a user application description. Processing device code is generated for a targeted processing device based at least in part on the user application description without user intervention, wherein the processing device code includes a system layer, wherein functionality of the system layer is independent of the targeted processing device.

Claims

1. A method, comprising:

generating a user application in response to user input, wherein the user application is described in a user application description; and

generating processing device code for a targeted processing device based at least in part on the user application description without user intervention, wherein the processing device code includes

a system layer, wherein functionality of the system layer is independent of the targeted processing device,

wherein the processing device code includes a hardware encapsulation layer to represent the targeted processing device to the system layer,

wherein the hardware encapsulation layer is generated based at least in part on the targeted processing device and wherein the hardware encapsulation layer comprises a low level driver configured to convert signals received from the targeted processing device to signals which the system layer can process.

2. The method of claim 1 wherein the system layer and the hardware encapsulation layer communicate using hardware independent interfaces.

3. The method of claim 1 wherein the processing device code includes a base project layer to support the hardware encapsulation layer, wherein the base project layer is generated based at least in part on the targeted processing device.

4. The method of claim 1 wherein generating the processing device code includes obtaining processing device code from libraries.

5. The method of claim 4, further comprising updating the libraries with new processing device code.

6. The method of claim 1, further comprising generating second processing device code for a second targeted processing device based at least in part on the user application description without user intervention, wherein the second targeted processing device is different than the targeted processing device, wherein the second processing device code includes a second system layer that is similar to the system layer.

7. The method of claim 1, further comprising performing a simulation of the user application, wherein the simulation is performed independent of the targeted processing device.

8. An article of manufacture, comprising:

a machine-readable storage medium storing a plurality of instructions which when executed perform operations comprising;

presenting a processing device maker graphical user interface (GUI) to allow a user to construct a user application using a processing device maker, wherein the user application is described in a user application description; and

generating processing device code for a targeted processing device based at least in part on the user application description without user intervention, wherein the processing device code includes

a system layer, wherein functionality of the system layer is independent of the targeted processing device,

wherein the processing device code includes a hardware encapsulation layer to represent the targeted processing device to the system layer,

wherein the hardware encapsulation layer is generated based at least in part on the targeted processing device and wherein the hardware encapsulation layer comprises a low level driver configured to convert signals received from the targeted processing device to signals which the system layer can process.

9. The article of manufacture of claim 8 wherein the system layer includes:

a transfer function to describe behavior of an output device of the targeted processing device; and

a driver associated with the output device.

10. The article of manufacture of claim 9 wherein the transfer function and the driver communicate using hardware independent application program interfaces.

11. The article of manufacture of claim 8 wherein the system layer communicates with the hardware encapsulation layer using hardware independent channels.

12. The article of manufacture of claim 8 wherein the processing device code includes a base project layer to operate at a register level of the targeted processing device to support the hardware encapsulation layer, wherein the base project layer is generated based at least in part on the targeted processing device.

13. The article of manufacture of claim 12 wherein the base project layer includes a user module to configure a portion of a block array of the targeted processing device.

14. The article of manufacture of claim 8 wherein execution of the plurality of instructions further perform operations comprising:

generating second processing device code for a second targeted processing device based at least in part on the user application description without user intervention, wherein the second targeted processing device is different than the targeted processing device, wherein the second processing device code includes the system layer, a second hardware encapsulation layer, and a second base project layer, wherein the second hardware encapsulation layer and the second base project layer are generated for the second targeted processing device.

15. A system, comprising:

a targeted processing device including a non-volatile storage device; and

a computer system coupled to the targeted processing device, the computer system having stored a plurality of instructions which when executed by the computer system perform operations comprising;

presenting a processing device maker graphical user interface (GUI) to allow a user to construct a user application using a processing device maker, wherein the user application is described in a user application description; and

generating processing device code for the targeted processing device based at least in part on the user application description without user intervention, wherein the processing device code includes

a system layer, wherein functionality of the system layer is independent of the targeted processing device and

wherein the processing device code further includes a hardware encapsulation layer and a base project layer, wherein the hardware encapsulation layer and the base project layer are generated based on the targeted processing device and wherein the hardware encapsulation layer comprises a low level driver configured to convert signals received from the targeted processing device to signals which the system layer can process.

16. The system of claim 15 wherein the system layer communicates with the hardware encapsulation layer using hardware independent channels.

17. The system of claim 15 wherein execution of the plurality of instructions further perform operations comprising:

compiling the processing device code into a binary image; and

loading the binary image into the non-volatile storage of the targeted processing device.