Method for forming voltage sustaining layer with opposite-doped islands for semiconductor power devices

• US 8,071,450 B2
• Filed: 01/16/2009
• Issued: 12/06/2011
• Est. Priority Date: 10/29/1993
• Status: Expired due to Fees

• Current Assignee: Third Dimension Semiconductor Incorporated
• Original Assignee: Third Dimension Semiconductor Incorporated
• Inventors: Chen, Xing-Bi
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US12/355,165
• Publication Number:
  US 20090130828A1
• Time in Patent Office: 1,054 Days
• Field of Search: 438139-140, 438268-269
• US Class Current: 438/269
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/73 Bipolar junction transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A method of manufacturing a semiconductor device includes preparing a semiconductor wafer with a substrate of a first conductivity type and forming a first epitaxial layer of the first conductivity type on the substrate. The first epitaxial layer has a first thickness. The method further includes growing a first oxide layer on the first epitaxial layer, masking the first oxide layer, ion implanting to create at least one embedded region of a second conductivity type in the first epitaxial layer, removing the first oxide layer, and forming a second epitaxial layer of the first conductivity type on the first epitaxial layer. The second epitaxial layer has the first thickness minus a thickness equal to a thickness of the at least one embedded region of the second conductivity type.

Claims

1. A method of manufacturing a semiconductor device comprising:

preparing a semiconductor wafer with a substrate of a first conductivity type;

forming a first epitaxial layer of the first conductivity type on the substrate, the first epitaxial layer having a first thickness;

growing a first oxide layer on the first epitaxial layer;

masking the first oxide layer;

ion implanting to create at least one first embedded region of a second conductivity type in the first epitaxial layer;

removing the first oxide layer;

forming a second epitaxial layer of the first conductivity type on the first epitaxial layer, the second epitaxial layer having a second thickness that is greater than the first thickness minus a thickness equal to a thickness, in a direction extending away from the substrate, of the at least one first embedded region of the second conductivity type;

growing a second oxide layer on the second epitaxial layer;

masking the second oxide layer;

ion implanting to create at least one second embedded region of a second conductivity type in the second epitaxial layer; and

removing the second oxide layer.

2. The method according to claim 1, wherein the first conductivity type is one of n-type and p-type and the second conductivity type is the other of n-type and p-type.

3. The method according to claim 1, wherein the substrate has a first doping concentration and the first epitaxial layer and the second epitaxial layer have a second doping concentration that is different from the first doping concentration.