Power and ground routing of integrated circuit devices with improved IR drop and chip performance

• US 8,072,004 B2
• Filed: 09/15/2010
• Issued: 12/06/2011
• Est. Priority Date: 03/21/2008
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Ko, Ching-Chung, Cheng, Tao, Liu, Tien-Yueh, Chou, Dar-Shii, Kao, Peng-Cheng
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US12/883,163
• Publication Number:
  US 20110001168A1
• Time in Patent Office: 447 Days
• Field of Search: 257/207, 257/758, 257/759, 257/765, 257/771, 257/E27.07
• US Class Current: 257/207
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer.

Claims

1. An integrated circuit chip comprising:

a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper;

a first passivation layer overlying said plurality of IMD layers and said plurality of first conductive layers;

a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying said first passivation layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and

a second passivation layer covering said second conductive layer and said first passivation layer.

2. The integrated circuit chip of claim 1, wherein said integrated circuit chip further comprises:

a plurality of second power/ground mesh wiring lines, formed in a topmost layer of said plurality of first conductive layers, for distributing power signal or ground signal;

wherein said second power/ground mesh wiring lines comprise a plurality of horizontal trace lines or longitudinal trace lines.

3. The integrated circuit chip of claim 2 wherein said plurality of first power/ground mesh wring line has a thickness that is greater than that of said second power/ground mesh wiring line.

4. The integrated circuit chip of claim 1 wherein said first power/ground mesh wiring lines comprise a plurality of horizontal trace lines or longitudinal trace lines.

5. The integrated circuit chip of claim 1, wherein said integrated circuit chip further comprises:

a first power/ground ring formed in said second conductive layer.

6. The integrated circuit chip of claim 1, wherein said integrated circuit chip further comprises:

a second power/ground ring formed in a topmost layer of said plurality of first conductive layers.

7. An integrated circuit chip comprising:

a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper;

a first passivation layer overlying said plurality of IMD layers and said plurality of first conductive layers;

a first power/ground ring, formed in a second conductive layer overlying said first passivation layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and

a second passivation layer covering said second conductive layer and said first passivation layer.

8. The integrated circuit chip of claim 7, wherein said integrated circuit chip further comprises:

a second power/ground ring, formed in a topmost layer of said plurality of first conductive layers, for distributing power signal or ground signal.

9. The integrated circuit chip of claim 8 wherein said first power/ground ring has a thickness that is greater than that of said second power/ground ring.

10. The integrated circuit chip of claim 7, wherein said integrated circuit chip further comprises:

a plurality of first power/ground mesh wiring lines, formed in said second conductive layer, for distributing power signal or ground signal;

wherein said plurality of first power/ground mesh wiring lines comprise a plurality of horizontal trace lines or longitudinal trace lines.

11. The integrated circuit chip of claim 7, wherein said integrated circuit chip further comprises:

a plurality of second power/ground mesh wiring lines, formed in a topmost layer of said plurality of first conductive layers, for distributing power signal or ground signal;

wherein said plurality of second power/ground mesh wiring lines comprise a plurality of horizontal trace lines or longitudinal trace lines.