System and method for photoemission-based defect detection

• US 8,072,589 B2
• Filed: 12/02/2008
• Issued: 12/06/2011
• Est. Priority Date: 01/18/2007
• Status: Expired due to Fees

• Current Assignee: DCG Systems Incorporated (Thermo Fisher Scientific Incorporated)
• Original Assignee: DCG Systems Incorporated (Thermo Fisher Scientific Incorporated)
• Inventors: Khurana, Neeraj
• Primary Examiner(s): Toatley, Gregory J
• Assistant Examiner(s): ALLI, IYABO
• Application Number:
  US12/326,859
• Publication Number:
  US 20090150098A1
• Time in Patent Office: 1,099 Days
• Field of Search: 3562371-2376, 702/57, 702/58, 702/85, 702/179
• US Class Current: 356/237.1
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

An IREM image of an IC is obtained. The emission intensity at each emission site is measured/calculated and is compared to reference intensity. The calculated intensity may be plotted against reference intensities. In general, the majority of the plotted intensities would lie in a given range within a straight line. However, for devices that exhibit an abnormal emission, the plot would result in an easily observable deviation from the line. The calculated intensity is used to make a determination of logical “1” or “0” for each device, which is automatically stored together with the corresponding test vector. The calculated logical states are then tabulated and compared against tabulation of reference logical states.

Claims

1. A method for detecting defective transistors in integrated circuit (IC) using photon emission, comprising:

obtaining an infrared emission microscopy image from an area of the IC;

determining intensity values to provide determined intensity of emission from each transistor present in the area of the IC;

obtaining reference intensity corresponding to each transistor;

comparing each determined intensity to corresponding reference intensity.

2. The method of claim 1, wherein the step of comparing comprises plotting each determined intensity against its corresponding reference intensity.

3. The method of claim 2, further comprising calculating a linear relationship between all of the determined intensities and the reference intensities.

4. The method of claim 3, further comprising determining a maximum allowable deviation from the linear relationship.

5. The method of claim 4, further comprising:

for each determined intensity, calculating deviation from the linear relationship and comparing the deviation to the maximum allowable deviation.

6. The method of claim 1, further comprising:

for each determined intensity assigning a logical state of “

one”

or “

zero”

.

7. The method of claim 6, further computing obtaining reference logical states and comparing the assigned logical states to the reference logical states.

8. The method of claim 1, further comprising:

assigning a first threshold;

for each transistor determining a difference between the determined intensity and the reference intensity;

determining whether the difference is below the first threshold and, if so, designating the transistor as suspect inoperative transistor.

9. The method of claim 8, further comprising:

assigning a second threshold;

for each transistor having a difference above the first threshold, comparing the difference to the second threshold and, if the difference is below the second threshold, designating the transistor as operative but malfunctioning transistor.

10. The method of claim 1, wherein calculating intensity comprises:

obtaining a CAD layout of the transistors present in the area of the IC;

generating a spread function for the transistors from a point spread function (PSF) of the optical system;

computing the intensity of discrete light emission of each transistor by comparing the spread function to light signal of the emission image.

11. The method of claim 10, further comprising:

determining a plurality of state combinations, each combination comprising unique mixture of states of the transistors;

for each of the plurality of state combinations;

generating a combination spread function;

comparing the combination spread function to the light signal to thereby obtain an error and discrete intensity of emission from each transistor;

selecting the state combination having the smallest error as the true state combination;

selecting the resulting intensities of states corresponding to the true state combination.

12. The method of claim 11, wherein comparing the combination spread function to the light signal further comprises performing a least square minimization operation on the combination spread function.

13. The method of claim 11, wherein comparing the combination spread function to the light signal further comprises performing a Chi-Square minimization operation on the combination spread function.

14. The method of claim 1, further comprising:

determining logical state for each calculated intensity;

storing the calculated state together with identity of a corresponding test vector.

15. The method of claim 14, further comprising comparing each logical state to a reference logical state.

16. A system for identifying malfunctioning and faulty transistors using IR photon emission collected from a device under test (DUT), comprising:

a first input receiving image signal correlating to the IR photon emission collected from a selected area of the DUT;

a processor receiving the image signal and determining emission intensity for each transistor within the selected area;

a storage having reference intensities stored therein;

a comparator comparing each of the determined emission intensities to a corresponding reference intensity;

an output circuit outputting the comparison results.

17. The system of claim 16, wherein said output circuit comprises a monitor displaying a plot of each determined emission intensity against a corresponding reference intensity.

18. The system of claim 17, further comprising a second input receiving CAD layout of the DUT and wherein said storage further having expected logical state for each transistor stored therein.

19. The system of claim 18, wherein said processor further assigns a logical state to each determined intensity and compares the assigned logical state to the expected logical state.

20. The system of claim 16, further comprising a state mapping module receiving the emission intensity for each device and determining a logical state for each device, and further storing the logical state and a corresponding test vector in the storage.

21. The system of claim 20, wherein the comparator compares the logic state of each transistor to an expected logical state.

22. An optical tester for testing a semiconductor device under test (DUT), comprising:

a collection optics for collecting infrared photon emission emitted from transistors within a selected area of the DUT;

a sensor for sensing the photon emission from the collection optics and generating an emission signal;

a processor receiving the emission signal and determining emission intensity for each transistor within the selected area;

a logic state module determining a logic state for each transistor;

a storage storing the logic state of each transistor together with a corresponding test vector.

23. The tester of claim 22, further comprising a state comparator comparing the logic state of each transistor to an expected logic state.

24. The tester of claim 23, further comprising:

reference intensities;

an intensity comparator comparing each of the determined emission intensities to a corresponding reference intensity;

an output circuit outputting the comparison results.

25. The system of claim 24, further comprising a monitor displaying a plot of each determined emission intensity against a corresponding reference intensity.