Physical layer repeater with discrete time filter for all-digital detection and delay generation

• US 8,078,100 B2
• Filed: 01/27/2006
• Issued: 12/13/2011
• Est. Priority Date: 10/15/2002
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Proctor, James A. Jr., Gainey, Kenneth M., Puig, Carlos M., Otto, James C., LaMont, Lawrence W. Jr.
• Primary Examiner(s): Vuong, Quochien B
• Application Number:
  US11/340,860
• Publication Number:
  US 20060195883A1
• Time in Patent Office: 2,146 Days
• Field of Search: 455/7, 455/9, 455/11.1, 455/15, 455/16, 455/18, 455/24, 455/67.11, 455/67.16, 455/85, 455/552.1, 455/307, 455/339, 370/315, 370/320, 370/328
• US Class Current: 455/11.1
• CPC Class Codes: H03H 15/00 Transversal filters electromechanical filters H03H9/46, H03H9/70
• CPC Class Codes: H03H 17/0275 comprising non-recursive filters
• CPC Class Codes: H03H 2017/0247 Parallel structures using a slower clock
• CPC Class Codes: H04B 7/155 Ground-based stations H04B7/204 takes precedence
• CPC Class Codes: H04B 7/15542 Selecting at relay station its transmit and receive resources selection of wireless resources by user or terminal H04W72/02; arrangements affording multiple use of the transmission path by two-dimensional division of the resources H04L5/0003, or by allocating sub-channels H04L5/003

Abstract

A discrete time bandpass filter element (103) having multiple stages (201, 202, 203, 204, 205) for use in a time division duplex radio protocol communications system including an automatic gain control. Discrete time bandpass filter is used to generate delay and can replace SAW filters in a wireless frequency translating repeater.

Claims

1. A repeater for conducting a repeating operation in an environment associated with a wireless network, the repeating operation including receiving a signal associated with a packet and transmitting the packet without modification of one or more of a source address and a destination address contained in the packet, the repeater comprising:

a digital baseband section including a signal processor and a detector; and

a processor coupled to and capable of controlling the baseband section, the processor configured to;

detect the presence of the signal associated with the packet on one of at least two frequency channels; and

delay the repeating operation using the signal processor,

wherein the signal processor includes a digital delay line and a digital filter and wherein the detection and delay are performed in parallel during the repeating operation.

2. The repeater according to claim 1, wherein the signal processor includes one or more of:

a preliminary filter stage configured to perform one of a decimation function and a delay function associated with the signal to provide a decimated signal;

an intermediate filter stage configured to perform a bandpass filtering of the decimated signal to provide a filtered signal; and

a terminal filter stage configured to provide one or more of an interpolation and a delay of the filtered signal to provide an output signal.

3. A repeater according to claim 2, wherein one of a sampling rate, a center frequency, a pass bandwidth, a stop bandwidth, a stop band attenuation, a group delay, and a frequency response associated with the one or more of the preliminary filter stage, the intermediate filter stage, and the terminal filter stage is adjustable.

4. A repeater in accordance with claim 2, wherein a stop band attenuation associated with the one or more of the preliminary filter stage, the intermediate filter stage, and the terminal filter stage is adjustable, wherein different predetermined stop band attenuation adjustment values are associated with different frequency ranges so as to reject known signals.

5. A repeater in accordance with claim 2, wherein a frequency response associated with the one or more of the preliminary filter stage, the intermediate filter stage, and the terminal filter stage is adaptive so as to minimize an error signal generated in the one or more of the preliminary filter stage, the intermediate filter stage, and the terminal filter stage.

6. A repeater in accordance with claim 1, wherein the digital delay line includes a continuous amplitude sampled delay line.

7. A repeater in accordance with claim 1, wherein the digital filter includes a continuous amplitude filter.

8. A repeater in accordance with claim 1, wherein the digital filter is coupled to one or more of a resistor ratio and a variable resistive structure, each including a Field Effect Transistor and being capable of generating a sum of weighted currents derived from an output of the digital delay line.

9. A repeater in accordance with claim 1, wherein:

the digital delay line generates a plurality of samples; and

the detector is coupled to the digital delay line in parallel with the digital filter, the detector configured to use the plurality of samples for the detection.

10. A repeater in accordance with claim 1, wherein the digital delay line is configured to compensate for a detection delay associated with the detector such that a control action associated with the repeater operation is capable of being performed prior to the signal being available at an output of the digital delay line.

11. A repeater in accordance with claim 1, wherein the detector includes one or more of a correlator, a power detector, and an automatic gain control circuit.

12. A repeater in accordance with claim 1, wherein the detector includes a power detector and an automatic gain control circuit, the power detector generates a power detection output signal, and wherein the automatic gain control circuit is configured to process the power detection output signal.

13. A discrete-time digital filter for a repeater repeating a signal associated with a packet in an RF digital communications environment, the discrete-time digital filter comprising:

a detection unit configured to receive a detection signal; and

a delay line configured to delay the repeating of the signal an amount of time sufficient to conduct at least one control function associated with the repeating,

wherein the detection unit and the delay line are configured to operate in parallel during the repeating.

14. A discrete-time digital filter in accordance with claim 13, further comprising:

a preliminary filter stage configured to provide one or more of a decimation and a delay of the transmit signal to provide a decimated transmit signal;

an intermediate filter stage configured to bandpass filter the decimated transmit signal to provide a filtered decimated transmit signal; and

a terminal filter stage configured to provide one or more of an interpolation and a delay of the filtered decimated transmit signal,

wherein the digital delay line and the detection unit are configured to operate in parallel with one or more of the preliminary filter stage, the intermediate filter stage, and the terminal filter stage.

15. A discrete-time filter in accordance with claim 14, wherein one of a sampling rate, a center frequency, a pass bandwidth, a stop bandwidth, a stop band attenuation, a group delay, and a frequency response associated with the one or more of the preliminary filter stage, the intermediate filter stage, and the terminal filter stage is adjustable.

16. A discrete-time filter in accordance with claim 14, wherein a stop band attenuation associated with the one or more of the preliminary filter stage, the intermediate filter stage, and the terminal filter stage is adjustable, wherein different predetermined stop band attenuation adjustments are associated with different frequency ranges so as to eliminate known interfering signals from the transmit signal.

17. A discrete-time filter in accordance with claim 14, wherein a frequency response associated with the one or more of the preliminary filter stage, the intermediate filter stage, and the terminal filter stage is adaptive so as to minimize an error signal generated in the one or more of the preliminary filter stage, the intermediate filter stage, and the terminal filter stage.

18. A discrete-time filter in a wireless repeater, comprising:

a digital detector,

a digital delay line; and

multiple filter stages including a decimating filter, an interpolating filter, and a single-rate filter,

wherein

the digital detector, the digital delay line, and the multiple filter stages are configured to operate in parallel, and

a passband associated with the discrete time filter is translated between a first frequency range and a second frequency range by multiplying a frequency characteristic associated with the decimating filter, the interpolating filter, and the single-rate filter by a periodic signal.

19. A repeater for conducting a repeating operation in an environment associated with a wireless network, the repeating operation including receiving a signal associated with a packet and transmitting the packet without modification of one or more of a source address and a destination address contained in the packet, the repeater comprising:

means for detecting the presence of the signal associated with the packet on one of at least two frequency channels; and

means for delaying the repeating operation using the signal processor, wherein the signal processor includes a digital delay line and a digital filter and wherein the detection and delaying performed by the means for detecting and the means for delaying, respectively, are performed in parallel during the repeating operation.

20. The repeater of claim 19 wherein the means for delaying delays the transmission of the packet an amount of time sufficient to conduct at least one control function associated with the repeating operation.

21. A method of operating a repeater to conduct a repeating operation in an environment associated with a wireless network, comprising:

receiving a signal associated with a packet;

detecting the presence of the signal associated with the packet on one of at least two frequency channels;

delaying a transmission of the packet; and

transmitting, after the delay, the packet without modification of one or more of a source address and a destination address contained in the packet,

wherein the detecting step and delaying step are performed in parallel.

22. The method of claim 21, wherein the delaying step delays the transmission of the packet an amount of time sufficient to conduct at least one control function associated with the repeating operation.