Fabrication method of power semiconductor structure with low gate charge

• US 8,080,457 B1
• Filed: 11/02/2010
• Issued: 12/20/2011
• Est. Priority Date: 07/23/2010
• Status: Active Grant

• Current Assignee: Super Group Semiconductor Co., Ltd.
• Original Assignee: Great Power Semiconductor Corp.
• Inventors: Hsu, Hsiu-Wen
• Primary Examiner(s): Ahmadi, Mohsen
• Application Number:
  US12/917,498
• Time in Patent Office: 413 Days
• Field of Search: 257/E21.384, 257/E21.396, 257/E21.4
• US Class Current: 438/259
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A fabrication method of a trenched power semiconductor structure with low gate charge is provided. Firstly, a substrate is provided. Then, a gate trench is formed in the substrate. Afterward, a dielectric layer is formed on the inner surfaces of the gate trench. Then, a spacer is formed on the dielectric layer covering the sidewall of the gate trench. Thereafter, a plug structure is formed in the space at the bottom of the gate trench, which is defined by the spacer. Then, a portion of the spacer is removed with the dielectric structure and the plug structure as an etching mask. Thereafter, a portion of the dielectric layer is removed with the remained spacer as an etching mask to expose the inner surface of the upper portion of the gate trench. Afterward, with the remained spacer being kept, a gate dielectric layer is formed on the inner surface of the upper portion of the gate trench, and then a polysilicon gate is filled into the upper portion of the gate trench.

Claims

1. A fabrication method of a trenched power semiconductor structure, comprising the steps of:

providing a substrate, which has a drain zone being defined therein;

forming a gate trench in the substrate;

forming a dielectric layer on inner surfaces of the gate trench;

forming a spacer covering the dielectric layer on a sidewall of the gate trench;

forming a polysilicon structure in a space at a bottom of the gate trench, and the space being defined by the spacer;

removing an unwanted portion of the spacer with the dielectric layer and the polysilicon structure as a mask by using etching back technology;

removing an unwanted portion of the dielectric layer with a remained portion of the spacer as an etching mask to expose the inner surface of an upper portion of the gate trench;

wherein the remained portion of the spacer being left on the sidewall of the gate trench;

forming a gate dielectric layer on the inner surface of the upper portion of the gate trench; and

forming a polysilicon gate in the upper portion of the gate trench;

wherein the polysilicon structure is used to increase a distance between the polysilicon gate and the drain zone;

wherein an upper edge of the spacer is located above an upper edge of the polysilicon structure.

2. The fabrication method of the trenched power semiconductor structure according to claim 1, wherein the step of removing the unwanted portion of the spacer is carried out by using etching back technology, such that an upper edge of the spacer is located below an upper edge of the plug structure.

3. The fabrication method of the trenched power semiconductor structure according to claim 1, wherein, the step of removing the unwanted portion of the dielectric layer is carried out by using etching back technology, such that an upper edge of the dielectric is located below an upper edge of the spacer.

4. The fabrication method of the trenched power semiconductor structure according to claim 1, wherein the dielectric layer is composed of silicon dioxide.

5. The fabrication method of the trenched power semiconductor structure according to claim 1, wherein the spacer is composed of silicon nitride.

6. The fabrication method of the trenched power semiconductor structure according to claim 1, wherein the plug structure is a dielectric structure.

7. The fabrication method of the trenched power semiconductor structure according to claim 6, wherein the dielectric structure is composed of silicon oxide.

8. The fabrication method of the trenched power semiconductor structure according to claim 1, after the step of forming the polysilicon structure, further comprising the step of forming at least a first dielectric layer on the polysilicon structure.