Method for mitigating imprint in a ferroelectric memory

• US 8,081,500 B2
• Filed: 03/31/2009
• Issued: 12/20/2011
• Est. Priority Date: 03/31/2009
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Ramtron International Corporation (Infineon Technologies AG)
• Inventors: Taylor, Craig, Chu, Fan, Sun, Shan
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US12/415,918
• Publication Number:
  US 20100246238A1
• Time in Patent Office: 994 Days
• Field of Search: 365/145, 365/49.12, 365/49.13, 365/65, 365/102, 365/117, 365/149, 365/230.06
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/223 using MOS with ferroelectric gate insulating film
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

An array of ferroelectric memory cells that allows imprint mitigation includes ferroelectric memory cells respectively coupled to word lines, plate lines, and bit lines; a word line driver for driving the word lines; a plate line driver for driving the plate lines; a bit line driver for driving the bit lines; and an isolation device driver for driving isolation devices coupled between the bit lines and a plurality of bit lines. The method for mitigating imprint includes coupling the bit lines to a respective plurality of sense amplifiers, turning on a word line and pulsing a plate line associated with a row of ferroelectric memory cells, disconnecting the bit lines from the respective sense amplifiers, driving the plate line low and the bit lines high, driving the plate line high and the bit lines low, driving the plate line low and floating the bit lines, driving the bit lines with the sense amplifier, and turning off the word line and precharging the bit lines. The method can be performed after each memory access, or can be performed whenever convenient with a counter and a rejuvenate command.

Claims

1. A method for mitigating imprint in an array of ferroelectric memory cells including a plurality of word lines, plate lines, and bit lines, each bit line connected with a sense amplifier through an isolation device, the method comprising:

storing original polarization states from a group of memory cells in respective sense amplifiers;

disconnecting the bit lines from the sense amplifiers by turning off the isolation devices;

switching the group of memory cells in the array from the original polarization states to first polarization states;

switching the group of memory cells in the array from the first polarization states to second polarization states that are opposite to the first polarization states; and

connecting the bit lines to the sense amplifiers by turning on the isolation devices to restore the original polarization states stored in the sense amplifiers into the group of memory cells.

2. The method of claim 1 wherein the original polarization states and the restored original polarization states comprise user data.

3. The method of claim 1 wherein the first polarization states of the group of memory cells comprise only ones or only zeroes.

4. The method of claim 1 wherein the second polarization states of the group of memory cells comprise only ones or only zeroes.

5. The method of claim 1 wherein keeping track of the ferroelectric memory cells subjected to the imprint mitigation method comprises the use of a non-volatile counter.

6. A ferroelectric memory array comprising:

a plurality of 1T/1C ferroelectric memory cells each having a bit line node, a plate line node, and a word line node;

a plurality of sense amplifiers, each of the sense amplifiers coupled to the bit line node of a respective one of the plurality of memory cells through an isolation device;

and a plurality of bit line isolation devices coupled between the bit line nodes of the memory cells, wherein the plate line nodes of each of the memory cells associated with a single bit line are coupled together.

7. The ferroelectric memory array of claim 6 wherein the word line nodes of the memory cells are coupled together.