Dual mode source follower for low and high sensitivity applications

• US 8,084,730 B2
• Filed: 12/10/2008
• Issued: 12/27/2011
• Est. Priority Date: 12/10/2008
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Vampola, John L., Kean, Bryan W.
• Primary Examiner(s): Legasse, Jr., Francis M
• Application Number:
  US12/332,132
• Publication Number:
  US 20100140452A1
• Time in Patent Office: 1,112 Days
• Field of Search: 250/208.1, 250/214.1, 250/214.R, 348/297, 348/299, 348/314, 257/431
• US Class Current: 250/214.R
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

In certain embodiments, a unit cell is provided. The unit cell may include a high sensitivity path and a low sensitivity path. The high sensitivity path may include a first transistor and a first switch. The first switch may couple an output node to the first transistor. The low sensitivity path may include a capacitor. A second switch may couple the high sensitivity path to the low sensitivity path. A third switch may couple the high sensitivity path and the low sensitivity path to a voltage node.

Claims

1. A unit cell, comprising:

a high sensitivity path comprising;

a first transistor; and

a first switch, the first switch coupled to an output node and the first transistor;

a low sensitivity path comprising;

a capacitor;

a second transistor; and

a fourth switch, the fourth switch coupled to the output node and the second transistor; and

wherein the high sensitivity path is coupled to the low sensitivity path using a second switch, the second switch is operable to isolate the low sensitivity path from the high sensitivity path, and the high sensitivity path and the low sensitivity path are coupled to a voltage node using a third switch.

2. The unit cell of claim 1, wherein the low sensitivity path is operable to store charge received in proportion to a detected light intensity.

3. The unit cell of claim 1, wherein the high sensitivity path is operable to store charge received in proportion to a detected light intensity.

4. The unit cell of claim 1, wherein the second switch is further operable to couple the high sensitivity path to the low sensitivity path when the high sensitivity path becomes saturated.

5. The unit cell of claim 1, wherein the second switch couples the high sensitivity path and the low sensitivity path when accumulated charge received in proportion to a detected light intensity is sufficient to cause the second switch to close.

6. The unit cell of claim 1, wherein:

the second switch is in a closed position;

the third switch is in an open position;

the fourth switch is in a closed position; and

a signal is read through the output node.

7. The unit cell of claim 1, wherein the low sensitivity path is isolated from the high sensitivity path and the voltage node after a predetermined amount of time has passed.

8. The unit cell of claim 1, wherein:

the second switch is in the closed position;

the third switch is in the closed position; and

charge is drained into the voltage node.

9. The unit cell of claim 1, wherein:

the second switch is in the open position;

the first switch is in the closed position; and

a signal is read though the output node.

10. The unit cell of claim 1, wherein:

the second switch is in the open position;

the first switch is in the open position; and

charge generated in response to a detected light intensity is accumulated at a first node.

11. The unit cell of claim 1, wherein:

the second switch is in a closed position;

the third switch is in an open position; and

charge generated in response to a detected light intensity is accumulated at the capacitor.

12. The unit cell of claim 1, wherein:

the second switch is in a closed position;

the third switch is in an open position;

the first switch is in a closed position; and

a signal is read though the output node.

13. The unit cell of claim 4, wherein the capacitor begins to store charge in response to the coupling of the high sensitivity path to the low sensitivity path when the high sensitivity path becomes saturated.

14. The unit cell of claim 4, wherein saturation occurs when an accumulated charge at the high sensitivity path exceeds a predetermined threshold.

15. A system for image capture, comprising:

an image sensor operable to generate an electric charge in proportion to a detected light intensity;

a unit cell coupled to the image sensor and operable to receive the electric charge, the unit cell comprising;

a high sensitivity path comprising;

a first transistor;

a first switch, the first switch coupled to an output node and the first transistor; and

a low sensitivity path comprising;

a capacitor;

a second transistor; and

a fourth switch, the fourth switch coupled to the output node and the second transistor;

wherein the high sensitivity path is coupled to the low sensitivity path using a second switch, the second switch is operable to isolate the low sensitivity path from the high sensitivity path, and the high sensitivity path and the low sensitivity path are coupled to a voltage node using a third switch; and

a signal processor coupled to the unit cell.