High mobility tri-gate devices and methods of fabrication

• US 8,084,818 B2
• Filed: 01/12/2006
• Issued: 12/27/2011
• Est. Priority Date: 06/30/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shaheen, Mohamad A., Doyle, Brian, Dutta, Suman, Chau, Robert S., Tolchinksy, Peter
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US11/332,189
• Publication Number:
  US 20100065888A1
• Time in Patent Office: 2,175 Days
• Field of Search: 257/64, 257/74, 257/255, 257/347, 257/368, 257/627, 257/797, 257/E23.179, 257/E29.004, 438/198
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76243 using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a <100> crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a <110> crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.

Claims

1. A high mobility semiconductor assembly comprising:

a first substrate having a first reference orientation located at a <

110>

crystal plane location on the first substrate;

a second substrate formed on top of the first substrate, the second substrate having a second reference orientation located at a <

100>

crystal plane location on the second substrate,

wherein the first reference orientation is aligned with the second reference orientation;

a non-planar device having a top surface and laterally opposite sidewalls formed in the second substrate, wherein each of the top surface and the laterally opposite sidewalls has a <

100>

crystal plane;

a gate dielectric formed on the top au ace and on the laterally opposite sidewalls;

a gate electrode formed adjacent the gate dielectric formed on the top of surface and on the laterally opposite sidewalls; and

a pair of source/drain regions formed on opposite sides of the gate electrode.

2. The high mobility semiconductor assembly of claim 1 wherein the non-planar device is a PMOS transistor.

3. The high mobility semiconductor assembly of claim 2 further comprising a non-planar NMOS transistor comprising:

a top surface and laterally opposite sidewalls formed in the second substrate, wherein each of the top surface and the laterally opposite sidewalls of the non-planar NMOS transistor has a <

100>

crystal plane;

a gate dielectric formed on the top surface and on the laterally opposite sidewalls;

a gate electrode formed adjacent the gate dielectric formed on the top of surface and on the laterally opposite sidewalls; and

a pair of source/drain regions formed on opposite sides of the gate electrode.

4. The high mobility semiconductor assembly of claim 3 wherein the non-planar NMOS transistor and non-planar PMOS transistor are aligned.

5. The high mobility semiconductor assembly of claim 1 wherein the first substrate has a <

100>

crystal plane top surface and the second substrate has a <

100>

crystal plane top surface.

6. The high mobility semiconductor assembly of claim 5 wherein the non-planar device is a PMOS transistor.

7. The high mobility semiconductor assembly of claim 6 further comprising a non-planar NMOS transistor comprising:

a top surface and laterally opposite sidewalls formed in the second substrate, wherein each of the top surface and the laterally opposite sidewalls of the non-planar NMOS transistor has a <

100>

crystal plane

a gate dielectric formed on the top surface and on the laterally opposite sidewalls;

a gate electrode formed adjacent the gate dielectric formed on the top of surface and on the laterally opposite sidewalls; and

a pair of source/drain regions formed on opposite sides of the gate electrode.

8. The high mobility semiconductor assembly of claim 7 wherein the non-planar NMOS transistor and non-planar PMOS transistor are aligned.