Multi-channel receiver architecture and reception method

• US 8,086,197 B2
• Filed: 11/12/2008
• Issued: 12/27/2011
• Est. Priority Date: 11/12/2008
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Doris, Konstantinos, Janssen, Erwin
• Primary Examiner(s): Cox, Cassandra
• Application Number:
  US12/269,302
• Publication Number:
  US 20100120386A1
• Time in Patent Office: 1,140 Days
• Field of Search: None
• US Class Current: 455/179.1
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03H 2218/08 Resource sharing
• CPC Class Codes: H04B 1/001 Channel filtering, i.e. selecting a frequency channel within the SDR system multiplexing of multicarrier modulation signals being represented by different frequencies H04L5/06; multiplexing of multicarrier modulation signals H04L5/023
• CPC Class Codes: H04B 1/0025 using a sampling rate lower than twice the highest frequency component of the sampled signal for demodulation of angle-modulated signals H03D3/006

Abstract

A multi-channel receiver comprising an ADC and a multi-band, multi-channel selector. The ADC converts a broad-band multi-channel signal into a digital signal. The digital signal is then broken into sub-bands each containing a plurality of channels. A channel selector selects desired channels from the appropriate sub-band. The multi-channel receiver may deliver simultaneous channels equal to the number of channel selectors that have been implemented. The multi-channel receiver may be implemented on a single integrated circuit.

Claims

1. A multi-channel receiver comprising:

an analog-to-digital converter (ADC) configured to convert using a sampling rate S an analog signal z which resides in a frequency band B Hz to a digital signal x, wherein digital signal x is representative of analog signal z; and

a multi-band selector circuit configured to receive the digital signal x and to map the digital signal x into M time domain sub-signals x₁ . . . x_M, wherein each sub-signal represents in a time domain a frequency domain content of digital signal x, wherein each sub-signal resides in a sub-range of band B, wherein each frequency component of digital signal x is represented at least in one of the sub-signals x₁ . . . x_M in its original form, and wherein each of the sub-signals x₁ . . . x_M has a sampling rate less than S, and the sub-ranges overlap.

2. The multi-channel receiver of claim 1, wherein the multi-band selector is further configured to map the digital signal x into M time domain sub-signals x₁ . . . x_M hierarchically.

3. The multi-channel receiver of claim 1 further comprising at least one channel selector connected to the output of the multi-band selector, and where in the channel selector is configured to select at least one channel out of any sub-signals x₁ . . . x_M.

4. The multi-channel receiver of claim 1, wherein the multi-band selector circuit comprises at least two signal branches, wherein at least one branch is a filter-bank, and wherein at least one branch is a digital frequency translator connected to another filter-bank.

5. The multi-channel receiver of claim 3, wherein the sub-ranges overlap at least by an amount equal to a channel width of the at least one channel selector.

6. The multi-channel receiver of claim 1, wherein the multi-band selector circuit comprises a plurality of processing branches corresponding to respective phases and an adder for adding branch signals from the processing branches, wherein at least two of the plurality of processing branches comprise:

a sub-sampler for sub-sampling sample values of the input signal at the phase corresponding to the branch;

a block realizing sign inversion of the sub-sampled values cyclically;

a filter comprising a first FIR filter, applied alternately to sets of sub-samples from the sub-sampler at even sub-sample positions and to sets at odd sub-sample positions, and a second FIR filter applied to further sets of sub-samples at odd and even sub-sample positions from the sub-sampler, when the first FIR filter is applied to the sets of sub-samples at even and odd sub-sample positions respectively; and

a combiner for combining output samples from the first and second FIR filter into the branch signals of the branch according to a combination pattern that changes cyclically as a function of sub-sample position and is responsive to a phase of the branch.

7. The multi-channel receiver of claim 1, wherein the ADC is selected from the group consisting of a time-interleaved ADC and a partitioned time-interleaved ADC.

8. The multi-channel receiver of claim 1, wherein the ADC is a partition time-interleaved ADC comprising:

a main signal input for inputting an analog signal into the circuit;

a front end circuitry comprising a plurality (N) of sampling units each having a signal input and a signal output, wherein the signal input of each of the sampling units is connected to said main signal input;

a backend circuitry comprising a plurality of demultiplexers each having a signal input and a group (K) of signal outputs;

a plurality (N) of groups (K) of ADC units each ADC unit having a signal input and a data output;

wherein;

the signal output of each sampling unit is connected to the signal input of one demultiplexer of said plurality of demultiplexers, and

the signal outputs of each demultiplexer are connected to the signal inputs of the ADC units of one group of ADC units, and

wherein said main signal input is configured to feed the analog signal to said plurality (N) of sampling units using time interleaving,

and wherein said demultiplexers are configured to feed the sampled signal to said plurality (N) of groups of ADC units using time interleaving.

9. The multi-channel receiver of claim 8, wherein at least one demultiplexer comprises an additional signal processing circuit.

10. The multi-channel receiver of claim 9, wherein the additional signal processing circuit is selected from the group consisting of a buffer, a follower, and an amplifier.

11. The multi-channel receiver of claim 8, wherein at least one ADC unit of said plurality of ADC units is configured to resample the sampled signal output by the respective sampling unit.

12. The multi-channel receiver of claim 8, wherein the ADC comprises a clock input configured to provide a first plurality of clock signals clocking the plurality of sampling units and a second plurality of clock signals clocking the plurality of groups of ADC units.

13. The multi-channel receiver of claim 11, wherein the ADC comprises a clock input configured to provide a first plurality of clock signals clocking the plurality of sampling units and a second plurality of clock signals clocking the plurality of groups of ADC units.

14. The multi-channel receiver of claim 8, wherein at least one signal conditioning unit is arranged between the main signal input and the signal inputs of the sampling units.

15. The multi-channel receiver of claim 14, wherein the at least one signal conditioning unit comprises at least one of a copier and a buffer.

16. The multi-channel receiver of claim 8, wherein the ADC further comprises a data recombination unit configured to recombine the data being output by the data outputs of the ADC units of said plurality of groups of ADC units so as to generate a one-dimensional digital data stream.

17. The multi-channel receiver of claim 6, wherein the combiner of a first one of the at least two of the plurality of branches is configured to form complex branch signals, a real part of the complex branch signal being formed from an output signal of the first and second FIR filter of the first one of the branches alternatingly, and an imaginary part of the complex branch signal being formed from the output signal of the second and first FIR filter of the first one of the branches when the real part is formed from the output signal of the first and second FIR filter respectively, the combiner of a second one of the at least two of the plurality of branches being configured to form the real and imaginary parts of the complex branch signal by summing and subtracting the output signal of the first and second FIR filter of the second one of the branches.

18. The multi-channel receiver of claim 3, further comprising one more channel decoders, wherein a channel decoder receives a channel signal from the channel selector.

19. The multi-channel receiver of claim 18, further comprising one or more source decoders, wherein a source decoder receives an output from a channel decoder.

20. The multi-channel receiver of claim 1, further comprising a signal processing unit, wherein the signal processing unit comprises an RF pre-processing unit, wherein the RF pre-processing unit receives a source signal and provides a processed signal to the ADC.

21. The multi-channel receiver of claim 20, where the RF pre-processing unit comprises at least one of a filter, a low-noise amplifier, a variable gain amplifier and an equalizer.

22. A multi-channel receiver comprising:

a signal processing unit, wherein the signal processing unit comprises an RF pre-processing unit, and wherein the RF pre-processing unit is configured to receive a source signal and to output a processed analog signal z which resides in a frequency band B Hz;

an analog-to-digital converter (ADC) connected to the signal processing unit and configured to convert analog signal z using a sampling rate S to a digital signal x, wherein digital signal x is representative of analog signal z;

a multi-band selector circuit configured to receive the digital signal x and to map the digital signal x into M time domain sub-signals x₁ . . . x_M, wherein each sub-signal represents in a time domain a frequency domain content of digital signal x, wherein each sub-signal resides in a sub-range of band B, wherein each frequency component of digital signal x is represented at least in one of the sub-signals x₁ . . . x_M in its original form, and wherein each of the sub-signals x₁ . . . x_M has a sampling rate less than S;

at least one channel selector connected to the output of the multi-band selector, and where in the at least one channel selector is configured to select at least one channel out of any sub-signals x₁ . . . x_M;

one or more channel decoders, wherein a channel decoder receives a channel signal from one of the at least one channel selectors; and

one or more source decoders, wherein a source decoder receives an output from a channel decoder.