Integrated circuit package system using interposer

• US 8,089,143 B2
• Filed: 09/16/2005
• Issued: 01/03/2012
• Est. Priority Date: 02/10/2005
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Lee, Myung Kil
• Primary Examiner(s): Im, Junghwa M
• Application Number:
  US11/162,635
• Publication Number:
  US 20060175695A1
• Time in Patent Office: 2,300 Days
• Field of Search: 257/686, 257/687, 257/678, 257/787, 257/E23.004, 438/109, 438/106, 438/107, 438/110
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An integrated circuit package system is provided in which an interposer of predetermined thickness including a central cavity is formed. Additionally, one or more contacts are formed around the central cavity on the interposer. The interposer is employed for connecting first and second packages.

Claims

1. A method of manufacture of an integrated circuit package system comprising:

forming an interposer of predetermined thickness to include a central cavity;

forming one or more contacts around the central cavity on the interposer, the contacts including solder balls in a solder resist on opposing sides of the interposer; and

employing the interposer for connecting a top and a bottom package.

2. The method of claim 1 further comprising:

forming the interposer substantially the same size as a bottom substrate of the bottom package; and

forming the central cavity large enough to contain a mold portion of the bottom package.

3. The method of claim 1 further comprising:

forming the interposer to allow for various chip thickness configurations, chip stacking configurations, or multiple vertical packages by stacking the interposer between each package.

4. The method of claim 1 further comprising:

forming an epoxy mold compound selected from the group consisting of normal and fine filler sizes around an integrated circuit chip.

5. The method of claim 1 further comprising:

forming electrical connections between one or more pads on an integrated circuit and one or more terminals on a substrate by wirebonding.

6. A method of manufacture of an integrated circuit package system comprising:

forming a bottom package with a mold portion;

forming an interposer over the bottom package with a central cavity and one or more contacts for electrically interconnecting the bottom package and a top package through the interposer, the contacts including solder balls in a solder resist on opposing sides of the interposer; and

forming the top package over the interposer.

7. The method of claim 6 further comprising:

forming the interposer substantially the same size as the bottom package; and

forming the central cavity large enough to contain the mold portion of the bottom package.

8. The method of claim 6 further comprising:

forming the interposer to allow for various chip thickness configurations, chip stacking configurations, or multiple vertical packages by stacking the interposer between each package.

9. The method of claim 6 further comprising:

forming one or more of the contacts to include organic solderability preservatives or solder on pad.

10. The method of claim 6 further comprising:

forming electrical connections between one or more pads and one or more terminals by wirebonding.

11. An integrated circuit package system comprising:

an interposer with a central cavity and predetermined thickness for connecting a bottom and a top package; and

one or more contacts formed around the cavity, the contacts including solder balls in a solder resist on opposing sides of the interposer.

12. The system of claim 11 further comprising:

the bottom package having a bottom substrate and a mold portion; and

wherein;

the interposer is substantially the same size as the bottom substrate; and

the central cavity is large enough to contain the mold portion of the bottom package.

13. The system of claim 11 further comprising:

two or more of the interposer to provide various chip thickness configurations, chip stacking configurations, or multiple vertical stacked package configurations.

14. The system of claim 11 further comprising:

one or more epoxy mold compounds selected from the group consisting of normal and fine filler sizes on at least one side of the interposer.

15. The system of claim 11 further comprising:

electrical connections wirebonded between one or more pads on an integrated circuit and one or more terminals on a substrate.

16. An integrated circuit package system comprising:

a bottom package with a mold portion;

a top package; and

an interposer with a central cavity between the bottom package and the top package, the interposer electrically interconnecting the bottom package and the top package by one or more contacts around the central cavity and connected through the interposer, the contacts including solder balls in a solder resist on opposing sides of the interposer.

17. The system of claim 16 wherein:

the interposer is substantially the same size as a bottom substrate; and

the central cavity is large enough to contain the mold portion of the bottom substrate.

18. The system of claim 16 further comprising:

a plurality of packages; and

a plurality of the interposer for providing various chip thickness configurations, chip stacking configurations, or multiple vertical packages by stacking the interposer between each of the plurality of packages.

19. The system of claim 16 further comprising:

one or more epoxy mold compounds selected from the group consisting of normal and fine filler sizes on the interposer.

20. The system of claim 16 wherein:

the one or more contacts on the interposer include organic solderability preservatives or solder on pad.