Charge accumulation capacitance sensor with linear transfer characteristic

• US 8,089,288 B1
• Filed: 11/16/2006
• Issued: 01/03/2012
• Est. Priority Date: 11/16/2006
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Maharita, Andrey
• Primary Examiner(s): Nguyen, Vincent Q
• Assistant Examiner(s): NGUYEN, HOAI AN D
• Application Number:
  US11/601,465
• Time in Patent Office: 1,874 Days
• Field of Search: 324/678, 324/676, 324/658, 324/649, 324/600, 324/686, 324/665, 324/672, 324/679, 324/519, 324/548, 324/76.66, 324/76.11
• US Class Current: 324/678
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G06F 3/03547 Touch pads, in which fingers can move on a surface
• CPC Class Codes: G06F 3/0445 using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer

Abstract

A method and apparatus for capacitance sensing uses an offset feedback voltage to linearize a charge-transfer characteristic.

Claims

1. An apparatus, comprising:

a first capacitor; and

a capacitance sensing circuit comprising a second capacitor selectively connectable to the first capacitor, wherein the capacitance sensing circuit is configured to transfer charge linearly from the first capacitor to the second capacitor for a plurality of cycles and to determine a value of the first capacitor;

a buffer amplifier comprising an input terminal and an output terminal, wherein the input terminal is coupled to the second capacitor; and

an adder to add an offset voltage to an output of the buffer amplifier, the adder comprising a first terminal and a second terminal, wherein the first terminal is coupled to the output terminal of the buffer amplifier and wherein the second terminal is selectively connectable to the first capacitor.

2. The apparatus of claim 1, wherein a first voltage on the first capacitor comprises a second voltage on the second capacitor plus the offset voltage when the second terminal of the adder is coupled to the first capacitor, and wherein charge is transferred linearly from the first capacitor to the second capacitor when the second capacitor is coupled to the first capacitor.

3. The apparatus of claim 1, further comprising:

a comparator to compare a second voltage on the second capacitor with a threshold voltage and to determine when the second voltage crosses the threshold voltage; and

a counter to provide a count of cycles of charge transfer required for the second voltage to cross the threshold voltage, wherein the value of the first capacitor is inversely proportional to the count.

4. The apparatus of claim 1, further comprising:

a counter to count a predetermined number of cycles of charge transfer; and

means for measuring a second voltage on the second capacitor after the predetermined number of cycles, wherein the value of the first capacitor is directly proportional to the second voltage.

5. The apparatus of claim 1, wherein the adder comprises a summing amplifier and an offset voltage source, wherein the offset voltage and a second voltage on the second capacitor are added to provide a first voltage on the first capacitor.

6. The apparatus of claim 5, wherein the first voltage and the second voltage are referenced to ground.

7. An apparatus, comprising:

a first capacitor; and

a capacitance sensing circuit comprising a second capacitor selectively connectable to the first capacitor, wherein the capacitance sensing circuit is configured to transfer charge linearly to the first capacitor from the second capacitor for a plurality of cycles;

a reference voltage selectively connectable to the second capacitor;

a buffer amplifier comprising an input terminal and an output terminal, wherein the input terminal is coupled to the second capacitor; and

a voltage source comprising a first terminal and a second terminal, wherein the first terminal is coupled to the output terminal of the buffer amplifier and wherein the second terminal is selectively connectable to the first capacitor.

8. The apparatus of claim 7, wherein the voltage source is configured to provide an offset voltage, wherein a first voltage on the first capacitor comprises a second voltage on the second capacitor minus the offset voltage when the second terminal of the voltage source is coupled to the first capacitor, and wherein charge is transferred linearly from the second capacitor to the first capacitor when the second capacitor is coupled to the first capacitor.

9. The apparatus of claim 7, further comprising:

a comparator to compare the second voltage on the second capacitor with a threshold voltage and to determine when the second voltage crosses the threshold voltage; and

a counter to provide a count of cycles of charge transfer required for the second voltage to cross the threshold voltage, wherein the value of the first capacitor is inversely proportional to the count.

10. The apparatus of claim 7, further comprising:

a counter to count a predetermined number of cycles of charge transfer; and

means for measuring the second voltage on the second capacitor after the predetermined number of cycles, wherein the value of the first capacitor is directly proportional to the second voltage.

11. The apparatus of claim 7, wherein the voltage source comprises a summing amplifier and an offset voltage source, wherein the offset voltage is subtracted from the second voltage on the second capacitor to provide the first voltage on the first capacitor.