Terminal apparatus

• US 8,090,398 B2
• Filed: 04/30/2008
• Issued: 01/03/2012
• Est. Priority Date: 10/09/1995
• Status: Expired due to Fees

• Current Assignee: SOTA Semiconductor LLC (Acacia Research Corporation)
• Original Assignee: Renesas Electronics Corporation
• Inventors: Nakagawa, Tetsuya, Hatano, Yuji, Sagesaka, Yasuhiro, Baji, Toru, Noguchi, Koki
• Primary Examiner(s): HANNON, CHRISTIAN A
• Application Number:
  US12/112,968
• Publication Number:
  US 20080207158A1
• Time in Patent Office: 1,343 Days
• Field of Search: 455/550.1, 455/557, 455/84, 712/35, 712/235
• US Class Current: 455/550.1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 15/7807 System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Claims

1. A mobile communications terminal comprising:

A microprocessor including registers and an internal memory;

an external memory coupled with the microprocessor;

an antenna configured to receive reception data from outside of the mobile communication terminal and to transmit data to outside of the mobile communication terminal;

a duplexer configured to separate an input radio wave of the reception data from an output radio wave of the transmit data, and coupled to the antenna,

a low-noise amplifier configured to input the reception data via the duplexer, and

an RF circuit configured to convert a frequency of the reception data input through the low-noise amplifier and the transmission data, wherein the internal memory includes a first internal memory and a second internal memory,

wherein the microprocessor is formed on a single chip semiconductor, and includes a CPU and a DSP,

wherein the CPU includes a part of the registers, and the DSP includes a part of the registers,

wherein the RF circuit is configured to convert the reception data from the low-noise amplifier into a low-frequency baseband analog signals,

wherein the reception data converted into the low-frequency is converted into digital data, and are provided to the DSP of the microprocessor,

wherein the DSP of the microprocessor is configured to decode the reception data of digital data, wherein the DSP of the microprocessor is configured to encode the transmit data,

wherein the transmit data encoded by the DSP of the microprocessor is converted into analog data,

wherein the transmit data of analog data is over an RF frequency by the RF circuit, and the transmit data from the RF circuit is provided the duplexer via a power amp,

wherein the microprocessor is operable to receive data from the internal memory to one of the registers for the CPU,

wherein the microprocessor is configured to receive data from the first and second internal memories to the registers for the DSP in parallel during encoding or decoding by the DSP,

wherein the microprocessor includes an external memory interface which provides a RAS signal and a CAS signal to the external memory for controlling the external memory, and

wherein the external memory is operable to be accessed by the CPU and DSP via the external memory interface.

2. A mobile communication terminal according to claim 1,

wherein the microprocessor further includes an interface circuit for providing a first data signal corresponding to the transmission data, and for receiving a second data signal corresponding to the receiving data.

3. A mobile communication terminal according to claim 2,

wherein the interface circuit has a storing unit for storing the receiving data and the transmission data.

4. A mobile communication terminal according to claim 1,

wherein the microprocessor is configured to output a first data signal corresponding to the transmission data to the antenna, and

wherein the microprocessor is operable to receive a second data signal corresponding to the reception data from the antenna.

5. A mobile communication terminal according to claim 1,

wherein the microprocessor is operable to perform a FIR filter operation per one cycle by using the DSP.

6. A mobile communication according to claim 5,

wherein the CPU includes an arithmetic logic unit, and

wherein the arithmetic logic unit is operable to perform an address operation for accessing to the internal memory by the CPU and the DSP.

7. A mobile communication terminal according to claim 1, wherein the external memory is operable to store a plurality of programs for using the DSP and the CPU.

8. A mobile communication terminal comprising:

a microprocessor formed on a single chip semiconductor, and including registers and an internal memory;

an external memory coupled to the microprocessor;

an antenna configured to receive a reception data from outside of the mobile communication terminal and to transmit transmission data to outside of the mobile communication terminal,

a duplexer configured to separate an input radio wave of the reception data from an output radio wave of the transmit data, and coupled to the antenna,

a LNA configured to input the reception data via the duplexer, and

an RF circuit configured to convert a frequency of the reception data via the LNA and the transmission data,

wherein the microprocessor includes a CPU, a DSP and an external memory interface,

wherein the CPU includes a part of the registers of the microprocessor,

wherein the DSP includes a part of the registers of the microprocessor,

wherein the RF circuit is configured to convert the reception data from the LNA into a low-frequency analog signals,

wherein the reception data converted into the low-frequency is converted into digital data, and are provided to the DSP of the microprocessor,

wherein the DSP of the microprocessor is configured to decode the reception data of digital data,

wherein the DSP of the microprocessor is configured to encode the transmit data,

wherein the transmit data encoded by the DSP is converted into analog data,

wherein the transmit data of analog data is over an RF frequency by the RF circuit, and outputted to outside via the antenna,

wherein the external memory interface provides a RAS signal, a CAS signal and address signals to the external memory for controlling the external memory is response to an access from the CPU or the DSP,

wherein the external memory is operable to provide data to the microprocessor based on the RAS signal and the CAS signal via the external memory interface, when the microprocessor operates a read access,

wherein the internal memory includes a first internal memory and a second internal memory, and

wherein the microprocessor is configured to receive data from the first and second internal memories to the registers of the DSP in parallel during encoding the transmit data or decoding the reception data.

9. A mobile communication terminal according to claim 8,

wherein the registers includes registers of the CPU and registers of the DSP,

wherein the microprocessor is operable to transfer data from the internal memory to the registers of the CPU, and

wherein the microprocessor is operable to transfer data from the memory to the registers of the DSP.

10. A mobile communication terminal according to claim 9,

wherein the DSP is configured to perform a FIR filter operation.

11. A mobile communication terminal according to claim 9,

wherein the microprocessor further has an arithmetic logic unit, and

wherein the arithmetic logic unit is operable to generate address signals for the DSP.

12. A mobile communication terminal according to claim 8,

wherein the microprocessor is configured to output a first data signal corresponding to the transmission data, to the antenna, and

wherein the microprocessor is configured to receive a second data signal corresponding to the reception data from the antenna.

13. A mobile communication terminal according to claim 8, wherein the external memory is operable to transfer data to the CPU and the DSP or receive data from the CPU and the DSP.

14. A mobile communication terminal according to claim 13,

wherein the CPU is operable to generate an address signal for the DSP, and

wherein the DSP is operable to access the external memory based on the address signal provided from the CPU.

15. A mobile communication terminal according to claim 8,

wherein the microprocessor further includes an interface circuit to provide a first data signal corresponding to the transmission data, and to receive a second data signal corresponding to the receiving data.

16. A mobile communication terminal according to claim 15,

wherein the interface circuit includes a storing unit to store the receiving data and the transmitting data.