Multiple chip module and package stacking method for storage devices

• US 8,093,103 B2
• Filed: 10/18/2010
• Issued: 01/10/2012
• Est. Priority Date: 12/29/2005
• Status: Active Grant

• Current Assignee: BiTMICRO, LLC (BiTMICRO Networks, Inc.)
• Original Assignee: BiTMICRO Networks, Inc.
• Inventors: Baylon, Joel Alonzo, Bugayong, Patrick Digamon, Bruce, Ricardo H., Bruce, Rey H.
• Primary Examiner(s): Ahmadi, Mohsen
• Application Number:
  US12/907,023
• Publication Number:
  US 20110038127A1
• Time in Patent Office: 449 Days
• Field of Search: 257/E21.613, 257/E21.661, 257/E21.662, 257/E21.526
• US Class Current: 438/109
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/1005 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1627 stacked type assemblies, e.g. stacked multi-cavities

Abstract

Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Claims

1. A method for stacking a plurality of modules, said plurality of modules including a first memory module and a second memory module;

said first memory module having a first surface and a second surface;

said second memory module having a third surface and a fourth surface;

said method comprising;

providing a first set of connections on said first memory module by;

forming a first active ball on said first surface,

forming a first set of passive balls on said first surface, said first set of passive balls including a first passive ball and a second passive ball, and

forming a first set of passive pads on said second surface, said first set of passive pads including a first passive pad and a second passive pad;

providing a second set of connections on said second memory module by;

forming a second active ball on said third surface, and

forming a third passive ball on said third surface, a third passive pad on said fourth surface;

connecting said first passive ball to said first passive pad, connecting said second passive ball to said second passive pad, and connecting said third passive ball to said third passive pad;

coupling said first passive pad to said second active ball by stacking said first memory module to said second memory module;

forming a first serial chain route that includes at least one serial chain connection, said serial chain connection including;

a serial chain circuit, a serial chain input, and serial chain output;

coupling said serial chain input with said serial chain output through said serial chain circuit;

forming a second serial chain route;

forming a control circuit for enabling a routing path that connects said first serial chain route with said second serial chain route within an end module; and

said control circuit is disposed to enable said routing path in response to a control input signal received from another module from the plurality of modules when said end module is coupled to said another module.

2. The method of claim 1, wherein:

said providing a first set of connections on said first memory module further includes placing said first passive ball at an offset distance from said first passive pad, and placing said second passive ball at said offset distance from said second passive pad; and

said providing a second set of connections on said second memory module further includes placing said third passive ball at said offset distance from said third passive pad.

3. The method of claim 2, wherein the plurality of modules includes a controller module that is disposed with an active pad;

and providing a ladder-like routing path from said active pad to said second active ball by causing said active pad connect with said first passive ball by stacking said controller module to said first memory module.

4. The method of claim 2:

wherein the plurality of modules includes a controller module that is disposed with an active pad;

wherein said providing a first set of connections on said first memory module further includes placing said first passive ball at a location that is opposite from said first passive pad, and placing said second passive ball at a location that is opposite from said second passive pad;

wherein said providing a second set of connections on said second memory module further includes placing said third passive ball at a location opposite from said third passive pad; and

further comprising;

providing a rotational routing path from said active pad to said second active ball by causing said active pad to connect with said first passive ball by stacking said controller module to said first memory module.

5. The method of claim 1, further comprising:

using a selectable buffer that extends a routing path of said first serial chain route within the first memory module.

6. The method of claim 1, further comprising the step of providing a selectable buffer disposed to create a routing path that includes said first serial chain route within the first memory module and said second serial chain route.

7. The method of claim 1, further comprising:

coupling a controller module to the first memory module.

8. The method of claim 1, further including:

using said first active ball as said first serial chain input and said first passive pad as said first serial chain output.

9. The method of claim 1, further comprising:

using said second active ball as said second serial chain input and said third passive pad as said second serial chain output;

disposing said second memory module with a selectable buffer that, if said second memory module does not have a third memory module from the plurality of module stacked on top of said second memory module, causes a signal traveling through said serial chain route to terminate at said third passive pad, and to route said signal to a third serial chain circuit.

10. The method of claim 9, further including:

coupling a main board to the plurality of modules, said main board having at least one active pad coupled to said serial chain route.

11. The method of claim 1, further including:

using the first module as said another module; and

using the second module as said end module.

12. A method for stacking a plurality of modules, said plurality of modules including a first memory module and a second memory module;

said first memory module having a first surface and a second surface;

said second memory module having a third surface and a fourth surface;

said method comprising;

forming one or more active ports on the first and second memory modules, said one or more active ports for carrying one or more active signals;

forming one or more passive ports on the first and second memory modules, said one or more passive ports for passing through said one or more active signals on the first and second memory modules;

coupling one of said active ports formed on said first memory module to one of said passive ports formed on said second memory module by stacking said first memory module to said second memory module;

forming a first serial chain route that includes at least one serial chain connection, said serial chain connection including;

a serial chain circuit, a serial chain input, and serial chain output;

coupling said serial chain input with said serial chain output through said serial chain circuit;

forming a second serial chain route;

forming a control circuit for enabling a routing path that connects said first serial chain route with said second serial chain route within an end module; and

said control circuit is disposed to enable said routing path in response to a control input signal received from another module from the plurality of modules when said end module is coupled to said another module.

13. The method of claim 12, further comprising:

using a selectable buffer that extends a routing path of said first serial chain route within the first memory module.

14. The method of claim 12, further comprising the step of providing a selectable buffer disposed to create a routing path that includes said first serial chain route within the first memory module and that further includes said second serial chain route.

15. The method of claim 12, further comprising:

coupling a controller module to the first memory module and using said second memory module as said end module.

16. The method of claim 12, further comprising:

adding to the plurality of modules a controller module that is disposed with an active pad; and

providing a ladder-like routing path that includes a connection between said active pad from said controller module and one of said passive ports by stacking said first memory module with said controller module.