Method and apparatus for on-demand power management

• US 8,095,818 B2
• Filed: 05/23/2008
• Issued: 01/10/2012
• Est. Priority Date: 12/21/2004
• Status: Expired due to Fees

• Current Assignee: Packet Digital, LLC
• Original Assignee: Packet Digital, LLC
• Inventors: Jorgenson, Joel A., Kakumanu, Divyata, Morlock, Brian M.
• Primary Examiner(s): Stoynov, Stefan
• Application Number:
  US12/126,216
• Publication Number:
  US 20080263382A1
• Time in Patent Office: 1,327 Days
• Field of Search: 713/322, 713/330, 713/501, 327/113, 455/127.1, 455/343.1, 455/574, 331/18, 331/25, 331/177.R
• US Class Current: 713/501
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system.

Claims

1. A method, comprising:

monitoring a processing demand in a processing system operating at a first one or more voltages and a first one or more clock frequencies phase-locked to a reference frequency;

wherein monitoring the processing demand comprises;

detecting a plurality of processing events, wherein the plurality of processing events comprise an average number of processing events per unit time; and

correlating a clock frequency requirement with the plurality of processing events, wherein correlating the clock frequency requirement with the plurality of processing events comprises comparing the average number of processing events per unit time with a current clock frequency;

generating a second one or more clock frequencies in response to the processing demand, the second one or more clock frequencies phase-locked to the reference frequency and phase-matched to the first one or more clock frequencies; and

switching from the first one or more clock frequencies to the second one or more clock frequencies without halting the processing system.

2. The method of claim 1, wherein generating the second one or more clock frequencies comprises:

determining values for the second one or more clock frequencies from the processing demand;

scaling the values of the second one or more clock frequencies to compensate for a system temperature and a processing variable;

synthesizing the scaled values of the second one or more clock frequencies; and

stabilizing the second one or more clock frequencies before switching from the first one or more clock frequencies.

3. The method of claim 2, wherein the processing variable is a process technology variable.

4. The method of claim 2, wherein the processing variable is a system specific calibration factor.

5. The method of claim 1, wherein a ratio of the second one or more clock frequencies to the first one or more clock frequencies is approximately up to six orders of magnitude.

6. The method of claim 1, further comprising:

generating a second one or more voltages in response to the processing demand; and

switching from the first one or more voltages to the second one or more voltages without halting the processing system.

7. The method of claim 6, wherein generating the second one or more voltages comprises:

determining values for the second one or more voltages from the processing demand;

scaling the values of the second one or more voltages to compensate for a system temperature and a processing variable;

setting the scaled values of the second one or more voltages; and

stabilizing the scaled values of the second one or more voltages before switching from the first one or more voltages.

8. The method of claim 7, wherein the processing variable is a process technology variable.

9. The method of claim 7, wherein the processing variable is a system specific calibration factor.

10. The method of claim 6, wherein switching from the first one or more voltages to the second one or more voltages comprises sequencing the second one or more voltages to reduce a transient power surge.