Method and apparatus for backside illuminated image sensors using capacitively coupled readout integrated circuits

• US 8,097,904 B2
• Filed: 09/07/2010
• Issued: 01/17/2012
• Est. Priority Date: 12/09/2008
• Status: Active Grant

• Current Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Original Assignee: Teledyne Scientific & Imaging, LLC (Teledyne Technologies Incorporated)
• Inventors: Eminoglu, Selim, Lauxtermann, Stefan C.
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US12/877,037
• Publication Number:
  US 20110215222A1
• Time in Patent Office: 497 Days
• Field of Search: 438/48, 438/54, 438 78- 79, 257225-234
• US Class Current: 257/228
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H04N 25/58 involving two or more exposures
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

The images sensor includes a readout circuit capacitatively coupled to a memory circuit. The readout circuit includes: (i) a photon detector to receive a plurality of photons and to provide a charge signal corresponding to the received photons, (ii) a resettable integrator that is reset multiple times over a single exposure time and provides an analog representation of the incident photons during the last integration cycle, and (iii) a comparator that monitors the integrator output and generates a reset pulse when the integrator reaches a built-in threshold value. The memory circuit includes: (i) a receiver circuit that detects the output of the digital driver in the front-end readout circuit via capacitive coupling and generates a digital voltage pulse for each received signal, and (ii) a digital counting memory to count the received pulses to provide a coarse digital representation of how many times the integrator is reset.

Claims

1. An active pixel image sensor (APS) configured to sense a photon received by a pixel surface, the APS comprising:

a first integrated circuit (IC) layer having a first back surface coupled to the pixel surface for receiving the photon, a first front surface having a first plate, and an analog device formed between the first back and front surfaces, the analog device coupled to the pixel surface and the first plate;

a second IC layer formed underneath the first IC layer, the second IC layer having second front and back surfaces and a digital device formed between the second front and back surfaces, the second front surface having a second plate configured to be capacitively coupled to the first plate of the first IC layer, the digital device coupled to the second plate of the second front surface; and

a passivation oxide layer coupled between the first and second plates, wherein the first and second plates and the passivation oxide layer form a capacitor between the first and second IC layers.

2. The APS of claim 1, further comprising a substrate, wherein the second IC layer is a first CMOS, layer formed on the substrate, the passivation oxide layer is formed on the second IC layer, and the first IC layer is a second CMOS layer formed on the passivation oxide layer.

3. The APS of claim 1, wherein the analog device of the first IC layer is configured to provide a fine analog representation of the received photon, and wherein the digital device of the second IC layer is configured to provide a coarse digital representation of the received photon.

4. The APS of claim 1, wherein the photon includes one or more photons, and wherein the analog device includes a photon detector configured to receive the one or more photons from the pixel surface and to convert the one or more photons to one or more charges.

5. The APS of claim 1, wherein:

the photon includes one or more photons,

the analog device is configured to convert the one or more photons to one more charges for a predefined exposure time, and

the analog device includes an integrator configured to generate a cumulative signal based on the one or more charges.

6. The APS of claim 1, wherein:

the photon includes one or more photons,

the analog device is configured to generate a cumulative signal based on the one or more photons and for a predefined exposure time, and

the analog device includes a comparator configured to generate a comparator output signal when the cumulative signal reaches a predefined threshold.

7. The APS of claim 6, wherein the analog device includes a reset logic configured to reset the cumulative signal based on the comparator output signal.

8. The APS of claim 1, wherein:

the photon includes one or more photons,

the analog device is configured to generate a comparator output signal when the one or more photons reach a predefined threshold, and the digital device includes a receiver capacitively coupled to the analog device, the

receiver is configured to receive the comparator output signal and generate one or more digital pulses based on the comparator output signal.

9. The APS of claim 8, wherein the digital device includes a counting memory coupled to the receiver, the counting memory is configured to count the one or more digital pulses.