Semiconductor device and method of shielding semiconductor die from inter-device interference

• US 8,101,460 B2
• Filed: 06/04/2008
• Issued: 01/24/2012
• Est. Priority Date: 06/04/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Limited
• Inventors: Pagaila, Reza A., Do, Byung Tai, Kuan, Heap Hoe, Huang, Rui
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): Brown, Valerie N
• Application Number:
  US12/133,216
• Publication Number:
  US 20090302435A1
• Time in Patent Office: 1,329 Days
• Field of Search: None
• US Class Current: 438/109
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/08146 : the bonding area connecting to a via connection in the body
• CPC Class Codes: H01L 2224/13025 : the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24137 : the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83851 : being an anisotropic conductive adhesive
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A plurality of stacked semiconductor wafers each contain a plurality of semiconductor die. The semiconductor die each have a conductive via formed through the die. A gap is created between the semiconductor die. A conductive material is deposited in a bottom portion of the gap. An insulating material is deposited in the gap and over the semiconductor die. A portion of the insulating material in the gap is removed to form a recess between each semiconductor die extending to the conductive material. A shielding layer is formed over the insulating material and in the recess to contact the conductive material. The shielding layer isolates the semiconductor die from inter-device interference. A substrate is formed as a build-up structure on the semiconductor die adjacent to the conductive material. The conductive material electrically connects to a ground point in the substrate. The gap is singulating to separate the semiconductor die.

Claims

1. A method of making a semiconductor device, comprising:

providing a first semiconductor wafer having a plurality of semiconductor die;

mounting a second semiconductor wafer having a plurality of semiconductor die over the first semiconductor wafer so that the plurality of semiconductor die in the first and second semiconductor wafers are aligned;

creating a gap between the aligned semiconductor die of the first and second semiconductor wafers;

depositing a conductive material in a bottom portion of the gap;

depositing an insulating material in the gap, over the conductive material, and over the aligned semiconductor die of the first and second semiconductor wafers;

removing a portion of the insulating material and a tapered portion of the conductive material in the gap to form a recess between each aligned semiconductor die of the first and second semiconductor wafers extending to the conductive material;

forming a shielding layer over the insulating material and in the recess that contacts the conductive material to isolate the aligned semiconductor die of the first and second semiconductor wafers with respect to inter-device interference;

forming a substrate with a build-up structure on the plurality of semiconductor die of the first semiconductor wafer adjacent to the conductive material;

electrically connecting the conductive material to a ground point in the substrate; and

singulating the first and second semiconductor wafers through the gap to separate the aligned semiconductor die of the first and second semiconductor wafers.

2. The method of claim 1, further including forming a conductive via in each semiconductor die of the first and second semiconductor wafer.

3. The method of claim 2, further including

electrically connecting one semiconductor die in the first semiconductor wafer to one semiconductor die in the second semiconductor wafer through the conductive via.

4. The method of claim 3, further including electrically connecting the shielding layer to the one semiconductor die in the second semiconductor wafer through the conductive via.

5. The method of claim 3, further including disposing a bonding agent between the conductive via in the one semiconductor die in the first semiconductor wafer and the conductive via in the one semiconductor die in the second semiconductor wafer to electrically connect the conductive via.

6. The method of claim 1, further including

forming conductive vias which extend through each aligned semiconductor die in the first and second semiconductor wafers to electrically connect the semiconductor die.

7. The method of claim 1, further including:

forming a conductive via in a periphery region of each semiconductor die of the first and second semiconductor wafers; and

electrically connecting one semiconductor die in the first semiconductor wafer to one semiconductor die in the second semiconductor wafer through the conductive via.

8. A method of making a semiconductor device, comprising:

providing a first semiconductor wafer having a plurality of semiconductor die;

creating a gap between the plurality of semiconductor die of the first semiconductor wafer;

depositing a conductive material in a bottom portion of the gap;

depositing an insulating material in the gap, over the conductive material, and over the plurality of semiconductor die of the first semiconductor wafer;

removing a portion of the insulating material and a portion of the conductive material in the gap to form a recess between the plurality of semiconductor die;

forming a shielding layer over the insulating material and in the recess to contact the conductive material and isolate the plurality of semiconductor die with respect to inter-device interference; and

singulating the first semiconductor wafer through the gap to separate the plurality of semiconductor die.

9. The method of claim 8, further including:

forming a substrate with a build-up structure on the plurality of semiconductor die adjacent to the conductive material; and

electrically connecting the conductive material to a ground point in the substrate.

10. The method of claim 8, further including:

disposing a second semiconductor wafer having a plurality of semiconductor die over the first semiconductor wafer prior to creating the gap;

forming a conductive via in each semiconductor die of the first and second semiconductor wafers; and

electrically connecting one semiconductor die in the first semiconductor wafer to one semiconductor die in the second semiconductor wafer through the conductive via.

11. The method of claim 10, further including disposing a bonding agent between the conductive via in the one semiconductor die in the first semiconductor wafer and the conductive via in the one semiconductor die in the second semiconductor wafer to electrically connect the conductive via.

12. The method of claim 10, further including electrically connecting the shielding layer to one of the plurality of semiconductor die in the second semiconductor wafer through the conductive via.

13. The method of claim 8, further including:

disposing a second semiconductor wafer having a plurality of semiconductor die over the first semiconductor wafer to align the plurality of semiconductor die in the first and second wafers prior to creating the gap; and

forming a conductive via which extends through each aligned semiconductor die in the first and second semiconductor wafers to electrically connect the semiconductor die.

14. The method of claim 10,

wherein the conductive via is formed in a periphery region of each semiconductor die of the first and second semiconductor wafers.

15. A method of making a semiconductor device, comprising:

creating a gap between a plurality of semiconductor die;

depositing a conductive material in a bottom portion of the gap;

depositing an insulating material in the gap, over the conductive material, and over the plurality of semiconductor die;

removing a portion of the insulating material in the gap to form a recess between each semiconductor die extending to the conductive material; and

forming a shielding layer over the insulating material and in the recess to contact the conductive material and isolate the plurality of semiconductor die with respect to inter-device interference.

16. The method of claim 15, further including:

forming a substrate with a build-up structure over the plurality of semiconductor die adjacent to the conductive material; and

electrically connecting the conductive material to a ground point in the substrate.

17. The method of claim 15, further including:

forming a conductive via in each of the plurality of semiconductor die;

stacking the plurality of semiconductor die prior to forming the gap; and

electrically connecting the stacked plurality of semiconductor die through the conductive via.

18. The method of claim 17, wherein

the conductive vias are formed in a periphery region of each semiconductor die.

19. The method of claim 15, further including:

stacking the plurality of semiconductor die within a semiconductor package; and

electrically connecting the plurality of semiconductor die to the semiconductor package bond wires or solder bumps.

20. A method of making a semiconductor device, comprising:

creating a gap between a plurality of semiconductor die;

depositing a conductive material in a bottom portion of the gap;

depositing an insulating material in the gap and over the plurality of semiconductor die; and

forming a shielding layer over the insulating material and in the gap to contact the conductive material and isolate the plurality of semiconductor die with respect to inter-device interference.

21. The method of claim 20, further including removing a portion of the insulating material in the gap to form a recess between each semiconductor die extending to the conductive material.

22. The method of claim 20, further including:

forming a substrate with a build-up structure over the plurality of semiconductor die adjacent to the conductive material; and

electrically connecting the conductive material to a ground point in the substrate.

23. The method of claim 20, further including:

forming a conductive via in each of the plurality of semiconductor die;

stacking the plurality of semiconductor die prior to forming the gap; and

electrically connecting the stacked plurality of semiconductor die through the conductive via.

24. The method of claim 20, further including:

stacking the plurality of semiconductor die within a semiconductor package; and

electrically connecting the plurality of semiconductor die to the semiconductor package bond wires or solder bumps.

25. The method of claim 20, wherein the plurality of semiconductor die are organized on a first and second semiconductor wafer.