Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines
First Claim
1. A memory array comprising:
- a semiconductor substrate;
sidewall structures arranged against inner surfaces of openings in sidewall material, wherein the sidewall structures have holes formed therein and wherein the openings are aligned generally with first data/bit lines;
a plurality of vertical extensions within the holes extending generally vertically from a surface of the semiconductor substrate, wherein the vertical extensions are aligned generally with the first data/bit lines;
gate structures formed about the vertical extensions such that the gate structures encompass at least a portion of the vertical extensions; and
second data/bit lines extending across the vertical extensions.
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Accused Products
Abstract
A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.
418 Citations
17 Claims
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1. A memory array comprising:
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a semiconductor substrate; sidewall structures arranged against inner surfaces of openings in sidewall material, wherein the sidewall structures have holes formed therein and wherein the openings are aligned generally with first data/bit lines; a plurality of vertical extensions within the holes extending generally vertically from a surface of the semiconductor substrate, wherein the vertical extensions are aligned generally with the first data/bit lines; gate structures formed about the vertical extensions such that the gate structures encompass at least a portion of the vertical extensions; and second data/bit lines extending across the vertical extensions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory array comprising:
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a semiconductor substrate; sidewall structures arranged against inner surfaces of openings, wherein the sidewall structures have holes formed therein and wherein the openings are aligned generally with first data/bit lines; a plurality of vertical extensions within the holes, wherein the vertical extensions are aligned generally with the first data/bit lines; gate structures about the vertical extensions; and second data/bit lines extending over the vertical extensions. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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Specification