Direct memory access controller system with message-based programming
First Claim
Patent Images
1. A message unit implementing message-based programming in a direct memory access controller, wherein the message unit comprises:
- a plurality of first-in-first-out (FIFO) memory queues, each queue being operable to store a plurality of data transfer request messages, each data transfer request message comprising a first address of a location in a source memory, a second address of a location in a destination memory, and a length of data to be transferred from the source memory to the destination memory;
an ASIC-side interface having a path to an DMA ASIC bus interface, the ASIC-side interface operable to provide address space decode for direct RAM access and the plurality of FIFO memory queues;
an DMA-side interface having a path to a plurality of DMA channels of a DMA controller, the DMA-side interface operable to notify the DMA channels of the data transfer request messages stored in the FIFO memory queues and provide access to the data transfer request messages;
a random access memory interface handling arbitration into the random access memory from the ASIC-side interface and the DMA-side interface, the arbitration from the ASIC-side interface including writing of incoming data transfer request message and debug access, the arbitration from the DMA-side interface including reading and loading of the data transfer request messages; and
a message module including pointers for a location of each of the plurality of FIFO memory queues, the message module operable to serialize pointer updates to manage multiple accesses,wherein the plurality of data transfer request messages are processed by the direct memory access controller to facilitate data transfer between the source memory and the destination memory.
8 Assignments
0 Petitions
Accused Products
Abstract
A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.
-
Citations
7 Claims
-
1. A message unit implementing message-based programming in a direct memory access controller, wherein the message unit comprises:
-
a plurality of first-in-first-out (FIFO) memory queues, each queue being operable to store a plurality of data transfer request messages, each data transfer request message comprising a first address of a location in a source memory, a second address of a location in a destination memory, and a length of data to be transferred from the source memory to the destination memory; an ASIC-side interface having a path to an DMA ASIC bus interface, the ASIC-side interface operable to provide address space decode for direct RAM access and the plurality of FIFO memory queues; an DMA-side interface having a path to a plurality of DMA channels of a DMA controller, the DMA-side interface operable to notify the DMA channels of the data transfer request messages stored in the FIFO memory queues and provide access to the data transfer request messages; a random access memory interface handling arbitration into the random access memory from the ASIC-side interface and the DMA-side interface, the arbitration from the ASIC-side interface including writing of incoming data transfer request message and debug access, the arbitration from the DMA-side interface including reading and loading of the data transfer request messages; and a message module including pointers for a location of each of the plurality of FIFO memory queues, the message module operable to serialize pointer updates to manage multiple accesses, wherein the plurality of data transfer request messages are processed by the direct memory access controller to facilitate data transfer between the source memory and the destination memory. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeAvago Technologies International Sales Pte Limited (Broadcom, Inc.)
-
Original AssigneeEmulex Design & Manufacturing Corp. (Broadcom, Inc.)
-
InventorsClayton, Shawn Adam, Fortin, Brian Mark, Willie, Daniel Brian, Wood, John Leland
-
Primary Examiner(s)Hafiz, Tariq
-
Assistant Examiner(s)VIDWAN, JASJIT S
-
Application NumberUS11/088,344Publication NumberTime in Patent Office2,505 DaysField of Search710/4, 710/7, 710/12, 710/31, 710/33, 710/40, 710/52US Class Current710/308CPC Class CodesG06F 11/1004 to protect a block of data ...G06F 13/28 using burst mode transfer, ...
