Task definition for specifying resource requirements

• US 8,108,656 B2
• Filed: 08/29/2002
• Issued: 01/31/2012
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Cornami, Inc.
• Original Assignee: QST Holdings LLC
• Inventors: Katragadda, Ramana, Spoltore, Paul, Howard, Ric
• Primary Examiner(s): CHEA, PHILIP J
• Application Number:
  US10/233,175
• Publication Number:
  US 20040054997A1
• Time in Patent Office: 3,442 Days
• Field of Search: 709/205, 709/226, 709/201, 718/105, 718/100, 718102-104, 712/28, 712/37
• US Class Current: 712/215
• CPC Class Codes: G06F 9/5044 considering hardware capabilities

Abstract

Task definitions are used by a task scheduler and prioritizer to allocate task operation to a plurality of processing units. The task definition is an electronic record that specifies researching needed by, and other characteristics of, a task to be executed. Resources include types of processing nodes desired to execute the task, needed amount or rate of processing cycles, amount of memory capacity, number of registers, input/output ports, buffer sizes, etc. Characteristics of a task include maximum latency tome, frequency of execution of a task, communication ports, and other characteristics. An exemplary task definition language and syntax is described that uses constructs including other of attempted scheduling operations, percentage or amount of resources desired by different operations, handling of multiple executable images or modules, overlays, port aliases and other features.

Claims

1. An integrated circuit comprising:

processing nodes that are heterogeneous between each other and comprise processing resources that are different between each other, wherein the processing nodes comprise programmable processors;

a memory that stores corresponding task definitions for different tasks to be executed by the processing nodes, the task definitions specifying processing resources for the different tasks, wherein the different tasks comprise programs for the programmable processors and the processing resources specified by the task definitions comprise program resources for executing the programs; and

a plurality of hardware schedulers in at least a portion of the processing nodes, each of the plurality of hardware schedulers in a different processing node, the hardware schedulers assigning the different tasks to the processing nodes for execution by matching the processing resources specified in the task definitions with the processing resources of the processing nodes.

2. The integrated circuit of claim 1, wherein the integrated circuit is in a consumer electronics device.

3. The integrated circuit of claim 1, wherein the integrated circuit is in a component of a consumer electronics device.

4. The integrated circuit of claim 1, wherein the processing nodes comprise configurable hardware and the processing resources specified by the task definitions comprise configuration information for configuring the configurable hardware for the different tasks.

5. The integrated circuit of claim 1, wherein the processing nodes comprise different types of processors.

6. The integrated circuit of claim 5, wherein the different types of processors include at least two of a general purpose processor, a special purpose processor, a digital signal processor, a RISC processor, and an ASIC processor.

7. The integrated circuit of claim 1, wherein the memory stores the different tasks and the different tasks include their corresponding task definitions.

8. The integrated circuit of claim 1, wherein the different tasks and the task definitions comprise computer program code.

9. The integrated circuit of claim 1, wherein the different tasks and their corresponding task definitions are located in common files stored in the memory.

10. The integrated circuit of claim 1, wherein the processing resources specified by the task definitions comprise required processing resources.

11. The integrated circuit of claim 1, wherein the processing resources specified by the task definitions comprise desired processing resources.

12. The integrated circuit of claim 1, wherein the processing resources specified by the task definitions specify processing node requirements or preferences for the different tasks.

13. The integrated circuit of claim 1, wherein the processing resources specified by the task definitions specify port requirements or preferences for the different tasks.

14. The integrated circuit of claim 1, wherein the processing resources specified by the task definitions specify buffer requirements or preferences for the different tasks.

15. The integrated circuit of claim 1, wherein the processing resources specified by the task definitions specify memory requirements or preferences for the different tasks.

16. The integrated circuit of claim 1, wherein the processing resources specified by the task definitions specify execution latency requirements or preferences for the different tasks.

17. The integrated circuit of claim 1, wherein the processing resources specified by the task definitions specify execution time requirements or preferences for the different tasks.

18. The integrated circuit of claim 1, wherein the processing resources specified by the task definitions specify execution frequency requirements or preferences for the different tasks.

19. The integrated circuit of claim 1, wherein the processing resources specified by the task definitions specify task loading requirements or preferences for the different tasks.

20. The integrated circuit of claim 1, further comprising:

a prioritizer that provides a priority for each task to be executed by the processing nodes and wherein the scheduler further assigns tasks by giving preference to higher-priority tasks when multiple tasks are simultaneously available for execution.

21. The integrated circuit of claim 1, further comprising:

an input/output system in communication with the memory and an external device for data exchange between the memory and the external device.

22. The integrated circuit of claim 1, further comprising:

storage resources in communication with the processing nodes and the scheduler.

23. The integrated circuit of claim 1, wherein at least one of the tasks is assigned to a plurality of the processing nodes for execution.

24. A method for scheduling tasks in an integrated circuit comprised of processing nodes that are heterogeneous between each other and comprise processing resources that are different between each other, the method comprising:

storing corresponding task definitions for different tasks to be executed by the processing nodes on the integrated circuit, the task definitions specifying processing resources for the different tasks, wherein the processing nodes comprise programmable processors, the different tasks comprise programs for the programmable processors, and the processing resources specified by the task definitions comprise program resources for executing the programs; and

assigning the different tasks to the processing nodes for execution on the integrated circuit from the integrated circuit comprising matching the processing resources specified in the task definitions with the processing resources of the processing nodes, wherein the different tasks are assigned by a plurality of hardware schedulers, each of the plurality of hardware schedulers in a different one of the processing nodes.

25. The method of claim 24, wherein the integrated circuit is in a consumer electronics device.

26. The method of claim 24, wherein the integrated circuit is a component of a consumer electronics device.

27. The method of claim 24, wherein the processing nodes comprise configurable hardware and the processing resources specified by the task definitions comprise configuration information for configuring the configurable hardware for the different tasks.

28. The method of claim 24, wherein the processing nodes comprise different types of processors.

29. The method of claim 28, wherein the different types of processors include at least two of a general purpose processor, a special purpose processor, a digital signal processor, a RISC processor, and an ASIC processor.

30. The method of claim 24, wherein the storing of corresponding task definitions comprises storing the different tasks wherein the different tasks include their corresponding task definitions.

31. The method of claim 24, wherein the different tasks and the task definitions comprise computer program code.

32. The method of claim 24, further comprising storing the different tasks and their corresponding task definitions in common files.

33. The method of claim 24, wherein the processing resources specified by the task definitions comprise required processing resources.

34. The method of claim 24, wherein the processing resources specified by the task definitions comprise desired processing resources.

35. The method of claim 24, wherein the processing resources specified by the task definitions specify processing node requirements or preferences for the different tasks.

36. The method of claim 24, wherein the processing resources specified by the task definitions specify port requirements or preferences for the different tasks.

37. The method of claim 24, wherein the processing resources specified by the task definitions specify buffer requirements or preferences for the different tasks.

38. The method of claim 24, wherein the processing resources specified by the task definitions specify memory requirements or preferences for the different tasks.

39. The method of claim 24, wherein the processing resources specified by the task definitions specify execution latency requirements or preferences for the different tasks.

40. The method of claim 24, wherein the processing resources specified by the task definitions specify execution time requirements or preferences for the different tasks.

41. The method of claim 24, wherein the processing resources specified by the task definitions specify execution frequency requirements or preferences for the different tasks.

42. The method of claim 24, wherein the processing resources specified by the task definitions specify task loading requirements or preferences for the different tasks.

43. The method of claim 24, wherein at least one of the tasks is assigned to a plurality of the processing nodes for execution.

44. An integrated circuit comprising:

processing nodes that are heterogeneous between each other and comprise processing resources that are different between each other, wherein the processing nodes comprise programmable processors, and wherein the processing nodes comprise configurable hardware;

a memory that stores corresponding task definitions for different tasks to be executed by the processing nodes, the task definitions specifying processing resources for the different tasks, wherein the different tasks comprise programs for the programmable processors and the processing resources specified by the task definitions comprise program resources for executing the programs, and wherein the processing resources specified by the task definitions comprise configuration information for configuring the configurable hardware for the different tasks; and

a plurality of hardware schedulers in at least a portion of the processing nodes, each of the plurality of hardware schedulers in a different processing node, the hardware schedulers assigning the different tasks to the processing nodes for execution by matching the processing resources specified in the task definitions with the processing resources of the processing nodes.