Reducing silicide resistance in silicon/germanium-containing drain/source regions of transistors
First Claim
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1. A method, comprising:
- forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure of a transistor;
forming a strain-inducing silicon/germanium alloy in said cavity, said silicon/germanium alloy having a first silicon concentration;
forming a silicon-containing semiconductor material on said strain-inducing silicon/germanium alloy, said silicon-containing semiconductor material having a second silicon concentration that is greater than said first silicon concentration and a germanium concentration that is less than approximately 5 atomic percent;
forming drain and source regions at least partially in said silicon/germanium alloy and said silicon-containing semiconductor material; and
forming a metal silicide in said silicon-containing semiconductor material.
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Abstract
In sophisticated P-channel transistors, a high germanium concentration may be used in a silicon/germanium alloy, wherein an additional semiconductor cap layer may provide enhanced process conditions during the formation of a metal silicide. For example, a silicon layer may be formed on the silicon/germanium alloy, possibly including a further strain-inducing atomic species other than germanium, in order to provide a high strain component while also providing superior conditions during the silicidation process.
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Citations
18 Claims
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1. A method, comprising:
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forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure of a transistor; forming a strain-inducing silicon/germanium alloy in said cavity, said silicon/germanium alloy having a first silicon concentration; forming a silicon-containing semiconductor material on said strain-inducing silicon/germanium alloy, said silicon-containing semiconductor material having a second silicon concentration that is greater than said first silicon concentration and a germanium concentration that is less than approximately 5 atomic percent; forming drain and source regions at least partially in said silicon/germanium alloy and said silicon-containing semiconductor material; and forming a metal silicide in said silicon-containing semiconductor material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method, comprising:
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forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure of a transistor; forming a strain-inducing silicon/germanium alloy in said cavity, said silicon/germanium alloy having a first silicon concentration; forming a silicon-containing semiconductor material on said strain-inducing silicon/germanium alloy, said silicon-containing semiconductor material comprising germanium and having a second silicon concentration that is greater than said first silicon concentration, wherein a germanium concentration of said silicon-containing semiconductor material is less than approximately 1 atomic percent; forming drain and source regions at least partially in said silicon/germanium alloy and said silicon-containing semiconductor material; and forming a metal silicide in said silicon-containing semiconductor material.
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13. A method, comprising:
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forming a silicon-containing semiconductor material on a silicon/germanium alloy formed in an active region of a P-type transistor, wherein forming said silicon-containing semiconductor material comprises incorporating an atomic species having a greater covalent radius than germanium into a silicon base material, said silicon-containing semiconductor material having a germanium concentration that is less than a germanium concentration of said silicon/germanium alloy; and forming a metal silicide locally restricted to said silicon-containing semiconductor material. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification