Error correction code generation method and memory control device

• US 8,127,205 B2
• Filed: 09/28/2007
• Issued: 02/28/2012
• Est. Priority Date: 12/27/2006
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hirano, Takahito, Miura, Takashi, Yamazaki, Iwao
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US11/864,057
• Publication Number:
  US 20080163029A1
• Time in Patent Office: 1,614 Days
• Field of Search: 714762-764, 714/768
• US Class Current: 714/768
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

A correct error correction code can be generated even if a RAM error occurs before writing store data in cache memory (RAM) after confirming that cache line data for storage includes no errors. Before writing the store data, cache line data for storage is stored in a register, the store data is written to the cache memory, the stored contents of the register are merged with the store data, and an error correction code is generated for a result of the merger.

Claims

1. An error correction code generation method, comprising:

storing data of a cache line on which a store data accompany with a store instruction is to be written to a register prior to writing the store data in a cache memory;

detecting an error of the data of the cache line to be written in the cache memory;

writing the store data that is confirmed to have no errors in the cache memory;

merging the data stored in the register with the store data in the cache memory accompany with the store instruction; and

generating an error correction code for a result of the merging.

2. The method according to claim 1, wherein

the merging merges the store data in the register with the store data accompany with the store instruction when a store instruction subsequent to the store instruction is a instruction for storing data on said cache line, the result of the merger corresponding to the store instruction is merged with the store data accompany with the subsequent store instruction, and

the generating generates an error correction code corresponding to the subsequent store instruction by using the result of the merging.

3. The method according to claim 2, wherein the cache memory is configured by random access memory.

4. The method according to claim 1, wherein the cache memory is configured by random access memory.

5. A cache memory control device, comprising:

a buffer that stores data in accordance with a store instruction;

a register that stores data of a cache line on which a data is to be written in accordance with store instruction, prior to writing the store data in a cache memory;

a detection unit that detects an error of the data of the cache line to be written in the cache memory;

a merge circuit that merges the data stored in the register with the data stored in the cache memory accompany with the store instruction; and

an error correction code generation circuit that generates an error correction code for a result of the merger, wherein the store data which is confirmed to have no errors is written in the cache memory.

6. The device according to claim 5, wherein

the merge circuit merges the stored data in the register with the store data accompany with the store instruction in response to a preceding store instruction in continuous store instructions to write data on a same cache line, and

the merge circuit merges the data merged accompany with the preceding store instruction with store data accompany with a subsequent store instruction.

7. The device according to claim 6, wherein the cache memory is configured by random access memory.

8. The device according to claim 5, wherein the cache memory is configured by random access memory.