Vertical light-emitting diode device structure with Si x N y layer

• US 8,129,237 B1
• Filed: 05/15/2008
• Issued: 03/06/2012
• Est. Priority Date: 05/15/2008
• Status: Active Grant

• Current Assignee: Semileds Optoelectronics Company Limited (SemiLEDs Inc)
• Original Assignee: Semileds Optoelectronics Company Limited (SemiLEDs Inc)
• Inventors: Tran, Chuong Anh
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): Garcia, Joannie A
• Application Number:
  US12/120,768
• Time in Patent Office: 1,391 Days
• Field of Search: 438/237, 438/328, 438/979, 438/FOR.157, 438/FOR.287, 438/FOR.416
• US Class Current: 438/237
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/025 Physical imperfections, e.g. particular concentration or distribution of impurities
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: Y10S 438/979 Tunnel diodes

Abstract

A vertical light-emitting diode (VLED) structure fabricated with a Si_xN_y layer responsible for providing increased light extraction out of a roughened n-doped surface of the VLED are provided. Such VLED structures fabricated with a Si_xN_y layer may have increased luminous efficiency when compared to conventional VLED structures fabricated without a Si_xN_y layer. Methods for creating such VLED structures are also provided.

Claims

1. A method of increasing light extraction from a vertical light-emitting diode (VLED) device, comprising:

depositing a first n-doped layer above a carrier substrate;

depositing a Si_xN_y mask above the first n-doped layer, wherein the Si_xN_y mask has openings exposing portions of the first n-doped layer;

depositing a second n-doped layer above the Si_xN_y mask such that the second n-doped layer is also deposited in the openings;

depositing an active layer for emitting light above the second n-doped layer;

depositing a p-doped layer above the active layer;

depositing one or more metal layers above the p-doped layer;

removing the carrier substrate;

removing the first n-doped layer and the Si_xN_y mask to expose a surface of the second n-doped layer; and

roughening the exposed surface of the second n-doped layer to increase light extraction from the roughened surface.

2. The method of claim 1, wherein depositing the Si_xN_y mask comprises in situ deposition.

3. The method of claim 2, wherein depositing the Si_xN_y mask comprises metal organic chemical vapor deposition (MOCVD) using a derivative of silane (Si_nH_2n+2) combined with NH₃.

4. The method of claim 1, wherein a growth temperature for depositing the Si_xN_y mask is 5 to 100°

C. higher than a growth temperature for depositing either the first n-doped layer or the second n-doped layer.

5. The method of claim 1, wherein roughening the exposed surface of the second n-doped layer comprises photoelectrochemical (PEC) oxidation and etching.

6. The method of claim 1, wherein a thickness of the first n-doped layer is in a range from about 0.1 to 10 microns.

7. The method of claim 1, wherein coverage of the Si_xN_y mask is chosen such that the second n-doped layer recovers after a growth thickness of 4 to 8 microns.

8. The method of claim 1, wherein depositing the Si_xN_y mask comprises depositing individual Si_xN_y areas through sputtering.

9. The method of claim 1, wherein depositing the Si_xN_y mask comprises:

depositing a continuous Si_xN_y layer; and

removing portions of the deposited continuous layer to form the openings in the Si_xN_y mask.

10. The method of claim 1, wherein the first n-doped layer, the second n-doped layer, and the p-doped layer comprise GaN.