Semiconductor device and method for producing the same

• US 8,129,273 B2
• Filed: 09/14/2010
• Issued: 03/06/2012
• Est. Priority Date: 04/25/2007
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Yoshizawa, Tetsuo, Urakawa, Shin-ichi, Miyake, Takashi
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US12/881,616
• Publication Number:
  US 20100330725A1
• Time in Patent Office: 539 Days
• Field of Search: 438/667, 438/668, 438/68, 438/110
• US Class Current: 438/667
• CPC Class Codes: H01L 21/566 Release layers for moulds, e.g. release layers, layers against residue during moulding
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01088 : Radium [Ra]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/18 : Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H05K 2201/09181 : Notches in edge pads
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence
• CPC Class Codes: H05K 3/42 : Plated through-holes or plated via connections

Abstract

In a semiconductor device which has through holes in an end face, in which a semiconductor element is fixedly mounted on a face of a substrate which has a wiring pattern, which is conductive to the wiring portion formed in the through hole, in at least one face, in which electrodes of the semiconductor element are electrically connected to the wiring pattern, and in which the face of the substrate which has the semiconductor element is coated with a resin, the through hole has a through hole land with a width of 0.02 mm or more, which is conductive to the wiring portion, in a substrate face, and the wiring portion and the through hole land are exposed.

Claims

1. A method of manufacturing a semiconductor device comprising steps of:

inserting, between upper and lower moldings disposed opposite to each other, a set of semiconductor devices each of which includes a plurality of semiconductor elements fixedly mounted along vertical columns and horizontal rows on a surface of a substrate having a wiring pattern electrically connected to a wiring portion formed in a through hole formed on the substrate, such that an electrode of each semiconductor element is electrically connected to the wiring pattern;

injecting a resin in a cavity between the upper and lower moldings holding the semiconductor elements, and curing the resin;

separating, from the upper and lower moldings, the set of semiconductor devices sealed within the resin;

cutting the substrate along the through hole, to be separated into each of the semiconductor devices, wherein the through hole has, on the surface of the substrate, a through hole land of a width of 0.02 mm or more electrically connected to the wiring portion, and at least one of the upper and lower moldings has a convex portion pressing the through hole at an area extending over a width of the through hole land, so that the resin does not flow into the through hole during the injecting of the resin.

2. A method according to claim 1, wherein a plurality of cavities between the upper and lower moldings are arranged along a plurality of columns, and cavities along one of the plurality of columns correspond to semiconductor elements of the plurality of semiconductor elements.

3. A method according to claim 2, wherein the cavities are arranged so that the cavities along the one of the plurality of columns contact with each other and have a gate at a contact portion, and the resin is injected through the gate into each of the cavities successively.

4. A method according to claim 1, wherein a release film is inserted into a cavity plane of at least one of the upper and lower moldings so that the molding or moldings into which the release film is inserted presses the through hole through the release film.