Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

• US 8,129,787 B2
• Filed: 03/22/2011
• Issued: 03/06/2012
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Brindle, Christopher N., Stuber, Michael A., Kelly, Dylan J., Kemerling, Clint L., Imthurn, George P., Welstand, Robert B., Burgener, Mark L.
• Primary Examiner(s): Nguyen, Dao H
• Assistant Examiner(s): Nguyen, Tram H
• Application Number:
  US13/053,211
• Publication Number:
  US 20110169550A1
• Time in Patent Office: 350 Days
• Field of Search: 257/105, 257/40, 257/347, 257/402, 257/403, 257/59, 257/61, 257/333, 257/337, 257/346, 257314-326, 455/333, 455/425, 455/550.1
• US Class Current: 257/347
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Claims

1. An RF switch circuit for switching RF signals, comprising:

a) an RF input port receiving an RF input signal;

b) an RF output port;

c) a switch transistor grouping having a first node coupled to the RF input port and a second node coupled to the RF output port, wherein the switch transistor grouping is controlled by a first switch control signal (C1); and

d) a shunt transistor grouping having a first node coupled to the RF input port and a second node coupled to ground, wherein the shunt transistor grouping is controlled by a second switch control signal (C1x), and wherein the shunt transistor grouping comprises one or more ACC MOSFETs;

wherein each ACC MOSFET includes a floating body and wherein the ACC MOSFET is biased to selectively operate in the accumulated charge regime, and wherein accumulated charge is present in the body of the floating body MOSFET when the MOSFET is biased to operate in the accumulated charge regime; and

wherein the ACC MOSFET further includes an accumulated charge sink (ACS) operatively coupled to the body of the MOSFET, and wherein, when the MOSFET is operated in the accumulated charge regime, an ACS bias voltage (V_ACS) is applied to the ACS to control the accumulated charge in the MOSFET body or to remove the accumulated charge from the MOSFET body via the ACS;

and wherein when the first switch control signal C1 is enabled, the switch transistor grouping is enabled and the shunt transistor grouping is disabled thereby passing the RF input signal through to the RF output port, and wherein when the second switch control signal C1x is enabled, the shunt transistor grouping is enabled while the switch transistor grouping is disabled thereby shunting the RF input signal to ground.

2. The RF switch of claim 1, wherein the switch transistor grouping comprises a single MOSFET, and wherein the shunt transistor grouping comprises a single ACC MOSFET.

3. The RF switch of claim 1, wherein the switch transistor grouping comprises a plurality of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a plurality of ACC MOSFETs arranged in a stacked configuration.

4. The RF switch of claim 3, wherein the switch transistor grouping comprises a first number of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a second number of ACC MOSFETs arranged in a stacked configuration, and wherein the first number and the second number differ from one another.

5. The RF switch of claim 1, wherein the ACC MOSFET includes a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS, and wherein the gate and ACS terminals are electrically coupled together and also coupled to the second switch control signal C1x, and wherein the accumulated charge is removed from the body of the ACC MOSFET through the ACS and gate terminals.

6. The RF switch of claim 5, wherein the switch transistor grouping comprises a single MOSFET, and wherein the shunt transistor grouping comprises a single ACC MOSFET.

7. The RF switch of claim 5, wherein the switch transistor grouping comprises a plurality of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a plurality of ACC MOSFETs arranged in a stacked configuration.

8. The RF switch of claim 5, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMD, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the body of the shunt transistor grouping.

9. The RF switch of claim 8, wherein the harmonic and intermodulation distortion of the RF signal output at the RF output port is reduced or eliminated by the removal or control of the accumulated charge from the body of the shunt transistor grouping.

10. The RF switch of claim 5, wherein a diode is coupled between the gate and ACS terminals such that the diode prevents positive current flow into the ACC MOSFET body when the ACC MOSFET is enabled and the diode is reverse-biased, and wherein the ACS terminal is coupled to the second switch control signal C1x via the diode, and wherein the accumulated charge is removed from the body of the ACC MOSFET through the ACS terminal.

11. The RF switch of claim 10, wherein the switch transistor grouping comprises a single MOSFET, and wherein the shunt transistor grouping comprises a single ACC MOSFET.

12. The RF switch of claim 1, wherein the switch transistor grouping comprises a plurality of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a plurality of ACC MOSFETs arranged in a stacked configuration.

13. The RF switch of claim 1, wherein the ACC MOSFET includes a gate terminal electrically coupled to the gate, a drain terminal electrically coupled to the drain, a source terminal electrically coupled to the source, and an ACS terminal electrically coupled to the ACS, and wherein the ACS terminal is electrically coupled to an accumulated charge sinking mechanism, and wherein the sinking mechanism comprises a control circuit adapted to control or remove the accumulated charge from the body when the shunt transistor grouping operates in the accumulated charge regime.

14. The RF switch of claim 13, wherein the switch transistor grouping comprises a single MOSFET, and wherein the shunt transistor grouping comprises a single ACC MOSFET.

15. The RF switch of claim 13, wherein the switch transistor grouping comprises a plurality of MOSFETs arranged in a stacked configuration, and wherein the shunt transistor grouping comprises a plurality of ACC MOSFETs arranged in a stacked configuration.

16. The RF switch of claim 13, wherein the ACS terminal of the shunt transistor grouping is coupled to a third switch control signal (C2), and wherein the shunt transistor grouping is enabled by the second switch control signal C1x while the switch transistor grouping is disabled thereby shunting the RF input signal to ground, and wherein the accumulated charge is removed from the body of the ACC MOSFET when the shunt transistor grouping is disabled.

17. The RF switch of claim 10, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMD, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the body of the shunt transistor grouping.

18. The RF switch of claim 13, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMD, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the body of the shunt transistor grouping.

19. The RF switch of claim 5, wherein the switch transistor grouping comprises one or more ACC MOSFETs defined by claim 1.

20. The RF switch of claim 10, wherein the switch transistor grouping comprises one or more ACC MOSFETs defined by claim 1.

21. The RF switch of claim 5, wherein the RF switch comprises a single-pole, multi-throw switch.

22. The RF switch of claim 10, wherein the RF switch comprises a single-pole, multi-throw switch.

23. The RF switch of claim 13, wherein the RF switch comprises a single-pole, multi-throw switch.

24. The RF switch of claim 5, wherein the RF switch comprises a multi-pole, single-throw switch.

25. The RF switch of claim 10, wherein the RF switch comprises a multi-pole, single-throw switch.

26. The RF switch of claim 13, wherein the RF switch comprises a multi-pole, single-throw switch.

27. The RF switch of claim 5, wherein the RF switch comprises a multi-pole, multi-throw switch.

28. The RF switch of claim 10, wherein the RF switch comprises a multi-pole, multi-throw switch.

29. The RF switch of claim 13, wherein the RF switch comprises a multi-pole, multi-throw switch.

30. The RF switch of claim 5, wherein the ACC MOSFET further includes a drain-to-source resistor (R_ds) electrically coupled between the drain and source of the ACC MOSFET.

31. The RF switch of claim 30, wherein the drain-to-source resistor (R_ds) provides a path between the ACC MOSFET drain and source whereby current associated with controlling the accumulate charge is conducted away from the source and drain when the ACC MOSFET is configured in series with other high impedance elements.

32. The RF switch of claim 31, wherein the gate of the ACC MOSFET is coupled to a gate resistor, and wherein the drain-to-source resistor (R_ds) has an impedance approximately equal to the impedance of the gate resistor.

33. The RF switch of claim 7, wherein the ACC MOSFETs further include a plurality of drain-to-source resistors (R_ds) associated with and respective to each of the stacked ACC MOSFETs, on a one-to-one basis, wherein each of the drain-to-source resistors are electrically coupled between the drain and source of each of their associated and respective ACC MOSFETs, and wherein the gates of each of the respective ACC MOSFETs are coupled to associated and respective gate resistors, and wherein the drain-to-source resistors (R_ds) of each associated and respective ACC MOSFET in the stack has an impedance approximately equal to the impedance of its associated and respective gate resistor divided by a number of ACC MOSFETs in the stack.

34. An RF switch circuit for switching RF signals, comprising:

a) a first input port receiving a first RF input signal (RF1);

b) a second input port receiving a second RF input signal (RF2);

c) an RF common port;

d) a first switch transistor grouping having a first node coupled to the first input port and a second node coupled to the RF common port, wherein the first switch transistor grouping is controlled by a first switch control signal (C1);

e) a second switch transistor grouping having a first node coupled to the second input port and a second node coupled to the RF common port, wherein the second switch transistor grouping is controlled by a second switch control signal (C1x);

f) a first shunt transistor grouping having a first node coupled to the second input port and a second node coupled to ground, wherein the first shunt transistor grouping is controlled by the first switch control signal C1; and

g) a second shunt transistor grouping having a first node coupled to the first input port and a second node coupled to ground, wherein the second shunt transistor grouping is controlled by the second switch control signal C1x;

wherein, when C1 is enabled, the first switch and first shunt transistor groupings are enabled while the second switch and shunt transistor groupings are disabled, thereby passing the first RF input signal RF1 through to the RF common port and shunting the second RF input signal RF2 to ground, and wherein when C1 is disabled and C1x is enabled, the second switch and shunt transistor groupings are enabled while the first switch and shunt transistor groupings are disabled, thereby passing the second RF input signal RF2 through to the RF common port and shunting the first RF input signal RF1 to ground, and wherein the switch and shunt transistor groupings comprise one or more ACC MOSFETs defined by claim 1.

35. The RF switch of claim 34, wherein each of the ACC MOSFETs include an ACS terminal in electrical communication with their respective and associated ACSs, and wherein the ACS terminals of each of the ACC MOSFETs are controlled by a sinking mechanism, and wherein the sinking mechanism removes accumulated charge from the ACC MOSFET bodies when the ACC MOSFETs operate in the accumulated charge regime.

36. The RF switch of claim 35, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMD, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the bodies of the ACC MOSFETs.

37. The RF switch of claim 35, wherein the ACC MOSFETs inherent drain-to-source breakdown voltage (BVDSS) characteristics, and wherein the BVDSS characteristics of the ACC MOSFETs are improved by removing or otherwise reducing the accumulated charge from the MOSFET bodies.

38. The RF switch of claim 35, wherein the RF switch exhibits small-signal performance characteristics including insertion loss, insertion phase (delay), and isolation, and wherein the small-signal performance characteristics of the RF switch are improved by removal and control of the accumulated charge from the ACC MOSFET bodies.

39. The RF switch of claim 35, wherein the RF switch includes associated temperature performance characteristics, and wherein the temperature performance characteristics of the RF switch are improved by removal and control of the accumulated charge from the ACC MOSFET bodies, and wherein the RF switch also exhibits decreased sensitivity to Vdd and fabrication process variations.

40. The RF switch of claim 34, wherein the RF switch comprises a single-pole, multi-throw switch.

41. The RF switch of claim 34, wherein the RF switch comprises a multi-pole, single-throw switch.

42. The RF switch of claim 34, wherein the RF switch comprises a multi-pole, multi-throw switch.

43. The RF switch of claim 1, wherein the ACC MOSFET is fabricated in a silicon-on-insulator technology.

44. The RF switch of claim 1, wherein the RF switch exhibits harmonic distortion, intermodulation distortion (IMD) and linearity performance characteristics under operation, and wherein the RF switch is capable of processing RF signals of a selected power level, and wherein the harmonic distortion, IMD, linearity characteristics, and power level processing of the RF switch are improved by removal or control of the accumulated charge from the body of the shunt transistor grouping.

45. The ACC MOSFET of claim 1, wherein the MOSFET comprises an enhancement mode PMOSFET device.

46. The ACC MOSFET of claim 1, wherein the MOSFET comprises a depletion mode PMOSFET device.

47. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated in a semiconductor-on-insulator technology.

48. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated on a semiconductor-on-sapphire substrate.

49. The ACC MOSFET of claim 47, wherein the semiconductor-on-insulator technology comprises silicon-germanium (SiGe) fabricated on an insulating substrate.

50. The ACC MOSFET of claim 47, wherein the semiconductor-on-insulator technology comprises gallium arsenide (GaAs) fabricated on an insulating substrate.

51. The ACC MOSFET of claim 1, wherein the MOSFET is fabricated in a semiconductor-on-bonded wafer technology.

52. The ACC MOSFET of claim 51, wherein the MOSFET is fabricated on direct silicon bond substrates by bonding and electrically attaching a film of single-crystal silicon onto a base insulating substrate.